Datasheet

5−15
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19−A12 of the end address.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: ExCA memory window 0 end-address low-byte
Offset: CardBus socket address + 812h; ExCA offset 12h
Register: ExCA memory window 1 end-address low-byte
Offset: CardBus socket address + 81Ah; ExCA offset 1Ah
Register: ExCA memory window 2 end-address low-byte
Offset: CardBus socket address + 822h; ExCA offset 22h
Register: ExCA memory window 3 end-address low-byte
Offset: CardBus socket address + 82Ah; ExCA offset 2Ah
Register: ExCA memory window 4 end-address low-byte
Offset: CardBus socket address + 832h; ExCA offset 32h
Type: Read/Write
Default: 00h
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the end address. In addition, the memory
window wait states are set in this register. See Table 5−12 for a complete description of the register contents.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: ExCA memory window 0 end-address high-byte
Offset: CardBus socket address + 813h; ExCA offset 13h
Register: ExCA memory window 1 end-address high-byte
Offset: CardBus socket address + 81Bh; ExCA offset 1Bh
Register: ExCA memory window 2 end-address high-byte
Offset: CardBus socket address + 823h; ExCA offset 23h
Register: ExCA memory window 3 end-address high-byte
Offset: CardBus socket address + 82Bh; ExCA offset 2Bh
Register: ExCA memory window 4 end-address high-byte
Offset: CardBus socket address + 833h; ExCA offset 33h
Type: Read-only, Read/Write
Default: 00h
Table 5−12. ExCA Memory Windows 0−4 End-Address High-Byte Registers Description
BIT SIGNAL TYPE FUNCTION
7−6 MEMWS RW
Wait state. Bits 7 and 6 specify the number of equivalent ISA wait states to be added to 16-bit memory
accesses. The number of wait states added is equal to the binary value of these two bits.
5−4 RSVD R Reserved. Bits 5 and 4 return 00b when read.
3−0 ENDHN RW
End-address high nibble. Bits 3−0 represent the upper address bits A23−A20 of the memory window end
address.