Datasheet

5−14
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19−A12 of the start address.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: ExCA memory window 0 start-address low-byte
Offset: CardBus socket address + 810h; ExCA offset 10h
Register: ExCA memory window 1 start-address low-byte
Offset: CardBus socket address + 818h; ExCA offset 18h
Register: ExCA memory window 2 start-address low-byte
Offset: CardBus socket address + 820h; ExCA offset 20h
Register: ExCA memory window 3 start-address low-byte
Offset: CardBus socket address + 828h; ExCA offset 28h
Register: ExCA memory window 4 start-address low-byte
Offset: CardBus socket address + 830h; ExCA offset 30h
Type: Read/Write
Default: 00h
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23−A20 of the start address. In addition, the memory
window data width and wait states are set in this register. See Table 5−11 for a complete description of the register
contents.
Bit 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0
Register: ExCA memory window 0 start-address high-byte
Offset: CardBus socket address + 811h; ExCA offset 11h
Register: ExCA memory window 1 start-address high-byte
Offset: CardBus socket address + 819h; ExCA offset 19h
Register: ExCA memory window 2 start-address high-byte
Offset: CardBus socket address + 821h; ExCA offset 21h
Register: ExCA memory window 3 start-address high-byte
Offset: CardBus socket address + 829h; ExCA offset 29h
Register: ExCA memory window 4 start-address high-byte
Offset: CardBus socket address + 831h; ExCA offset 31h
Type: Read/Write
Default: 00h
Table 5−11. ExCA Memory Windows 0−4 Start-Address High-Byte Registers Description
BIT SIGNAL TYPE FUNCTION
7 DATASIZE RW
Data size. Bit 7 controls the memory window data width. This bit is encoded as:
0 = Window data width is 8 bits (default)
1 = Window data width is 16 bits
6 ZEROWAIT RW
Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing
emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8- and 16-bit cycles have standard length (default)
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
16-bit cycles are reduced to equivalent of two ISA cycles.
5−4 SCRATCH RW Scratch pad bits. Bits 5 and 4 have no effect on memory window operation.
3−0 STAHN RW
Start-address high nibble. Bits 3−0 represent the upper address bits A23−A20 of the memory window
start address.