Datasheet
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Electrical Characteristics
I
2
C Interface Timing Requirements
PCF8575C
REMOTE 16-BIT I
2
C AND SMBus LOW-POWER I/O EXPANDER
WITH INTERRUPT OUTPUT
SCPS123E – MARCH 2005 – REVISED OCTOBER 2007
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
4.5 V to
V
IK
Input diode clamp voltage I
I
= – 18 mA – 1.2 V
5.5 V
V
POR
Power-on reset voltage
(2)
V
I
= V
CC
or GND, I
O
= 0 V
POR
1.2 1.8 V
I
OHT
P-port transient pullup current High during ACK V
OH
= GND 4.5 V – 0.5 – 1 mA
4.5 V to
SDA V
OL
= 0.4 V 3
5.5 V
V
OL
= 0.4 V 5 15
4.5 V to
I
OL
P port mA
5.5 V
V
OL
= 1 V 10 25
4.5 V to
INT V
OL
= 0.4 V 1.6
5.5 V
SCL, SDA ± 2
4.5 V to
I
I
V
I
= V
CC
or GND μ A
5.5 V
A0, A1, A2 ± 1
4.5 V to
I
IHL
P port V
I
≥ V
CC
or V
I
≤ GND ± 400 μ A
5.5 V
Operating mode V
I
= V
CC
or GND, I
O
= 0, f
SCL
= 400 kHz 100 200
I
CC
5.5 V μ A
Standby mode V
I
= V
CC
or GND, I
O
= 0, f
SCL
= 0 kHz 2.5 10
One input at V
CC
– 0.6 V, 4.5 V to
Δ I
CC
Supply current increase 200 μ A
Other inputs at V
CC
or GND 5.5 V
4.5 V to
C
i
SCL V
I
= V
CC
or GND 3 7 pF
5.5 V
SDA 3 7
4.5 V to
C
io
V
IO
= V
CC
or GND pF
5.5 V
P port 4 10
(1) All typical values are at V
CC
= 5 V, T
A
= 25 ° C.
(2) The power-on reset circuit resets the I
2
C bus logic with V
CC
< V
POR
and sets all I/Os to logic high (with current source to V
CC
).
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6 )
MIN MAX UNIT
f
scl
I
2
C clock frequency 400 kHz
t
sch
I
2
C clock high time 0.6 μ s
t
scl
I
2
C clock low time 1.3 μ s
t
sp
I
2
C spike time 50 ns
t
sds
I
2
C serial-data setup time 100 ns
t
sdh
I
2
C serial-data hold time 0 ns
t
icr
I
2
C input rise time 20 + 0.1C
b
(1)
300 ns
t
icf
I
2
C input fall time 20 + 0.1C
b
(1)
300 ns
t
ocf
I
2
C output fall time (10-pF to 400-pF bus) 300 ns
t
buf
I
2
C bus free time between stop and start 1.3 μ s
t
sts
I
2
C start or repeated start condition setup 0.6 μ s
t
sth
I
2
C start or repeated start condition hold 0.6 μ s
t
sps
I
2
C stop condition setup 0.6 μ s
t
vd
Valid-data time SCL low to SDA output valid 1.2 μ s
C
b
I
2
C bus capacitive load 400 pF
(1) C
b
= total bus capacitance of one bus line in pF
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