Datasheet

14
I/O
Port
4
5
6
7
9
10
11
12
P0
P1
P2
P3
P4
P5
P6
P7
Shift
Register
8 Bit
LP Filter
Interrupt
Logic
I
2
C Bus
Control
Input
Filter
15
Power-On
Reset
Read Pulse
Write Pulse
PCF8574
3
2
1
13
16
8
GND
V
CC
SDA
SCL
A2
A1
A0
INT
Pin numbers shown are for the DW and N packages.
To Interrupt
Logic
P0−P7
V
CC
GND
C
I
S
D Q
FF
C
I
S
D Q
FF
Write Pulse
Data From
Shift Register
Power-On
Reset
Read Pulse
Data to
Shift Register
100 µA
PCF8574
www.ti.com ............................................................................................................................................................... SCPS068G – JULY 2001 – REVISED MAY 2008
LOGIC DIAGRAM (POSITIVE LOGIC)
SIMPLIFIED SCHEMATIC DIAGRAM OF EACH P-PORT INPUT/OUTPUT
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Product Folder Link(s): PCF8574