Datasheet

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To Interrupt
Logic
P0 to P7
V
CC
GND
C
I
S
D Q
FF
C
I
S
D Q
FF
Write Pulse
Data From
Shift Register
Power-On
Reset
Read Pulse
Data To
Shift Register
100 µA
I
2
C Interface
PCF8574A
REMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
SIMPLIFIED SCHEMATIC DIAGRAM OF EACH P-PORT INPUT/OUTPUT
I
2
C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent,
most-significant bit (MSB) first, including the data direction bit (R/ W). This device does not respond to the general
call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA
I/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
The data byte follows the address acknowledge. If the R/ W bit is high, the data from this device are the values
read from the P port. If the R/ W bit is low, the data are from the master, to be output to the P port. The data byte
is followed by an acknowledge sent from this device. If other data bytes are sent from the master, following the
acknowledge, they are ignored by this device. Data are output only if complete bytes are received and
acknowledged. The output data will be valid at time, t
pv
, after the low-to-high transition of SCL and during the
clock cycle for the acknowledge.
A stop condition, a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the master.
Interface Definition
BIT
BYTE
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I
2
C slave address L H H H A2 A1 AO R/ W
I/O data bus P7 P6 P5 P4 P3 P2 P1 P0
3