Datasheet

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
14
I/O
Port
4
5
6
7
9
10
11
12
P0
P1
P2
P3
P4
P5
P6
P7
Shift
Register
8 Bit
LP Filter
Interrupt
Logic
Input
Filter
15
Power-On
Reset
Read Pulse
Write Pulse
PCF8574A
3
2
1
13
16
8
GND
V
CC
SDA
SCL
A2
A1
A0
INT
Pin numbers shown are for the DW and N packages.
I
2
C Bus
Control
PCF8574A
REMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
The PCF8574A provides an open-drain output ( INT) that can be connected to the interrupt input of a
microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After
time, t
iv
, INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed
to the original setting or data is read from, or written to, the port that generated the interrupt. Resetting occurs in
the read mode at the acknowledge bit after the rising edge of the SCL signal, or in the write mode at the
acknowledge bit after the high-to-low transition of the SCL signal. Interrupts that occur during the acknowledge
clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of
the I/Os after resetting is detected and, after the next rising clock edge, is transmitted as INT. Reading from, or
writing to, another device does not affect the interrupt circuit.
By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I
2
C bus. Therefore, the PCF8574A can remain a simple slave
device.
LOGIC DIAGRAM (POSITIVE LOGIC)
2