Datasheet
1
I/O
Port
Shift
Register
8 Bits
Input
Filter
2
Power-On
Reset
Read Pulse
Write Pulse
5
4
3
16
8
GND
V
CC
SDA
SCL
A2
A1
A0
I
2
C-Bus
Control
P7−P0
RESET
15
PCA9557
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.................................................................................................................................................... SCPS133I – DECEMBER 2005 – REVISED JUNE 2008
LOGIC DIAGRAM (POSITIVE LOGIC)
A. Pin numbers shown are for the D, DB, DGV, PW, and RGY packages.
B. All I/Os are set to inputs at reset.
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