Datasheet

V
C
C
CLK
D
Q
FF
Configuration
Register
Data From
Shift Register
Data From
Shift Register
Q
Write Configuration
Pulse
CLK
D
Q
FF
Q
Write Pulse
Output Port
Register
100 kW
Q1
Q2
GND
I/O Pin
Output Port
Register Data
CLK
D
Q
FF
Q
Input Port
Register
Read Pulse
CLK
D
Q
FF
Q
Polarity Inversion
Register
Write Polarity
Pulse
Input Port
Register Data
Polarity
Register Data
To INT
Data From
Shift Register
I/OPort
PCA9555
www.ti.com .........................................................................................................................................................SCPS131E–AUGUST2005–REVISEDMAY2008
SIMPLIFIEDSCHEMATICOFP-PORTI/Os
(1)
(1)Atpower-onreset,allregistersreturntodefaultvalues.
WhenanI/Oisconfiguredasaninput,FETsQ1andQ2areoff,creatingahigh-impedanceinput.Theinput
voltagemayberaisedaboveV
CC
toamaximumof5.5V.
IftheI/Oisconfiguredasanoutput,Q1orQ2isenabled,dependingonthestateoftheOutputPortregister.In
thiscase,therearelow-impedancepathsbetweentheI/OpinandeitherV
CC
orGND.Theexternalvoltage
appliedtothisI/Opinshouldnotexceedtherecommendedlevelsforproperoperation.
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Not Recommended for New Designs