Datasheet

SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
PCA9554
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AStopcondition,alow-to-hightransitionontheSDAinput/outputwhiletheSCLinputishigh,issentbythe
master(seeFigure1).
Anynumberofdatabytescanbetransferredfromthetransmittertothereceiverbetweenthestartandthestop
conditions.EachbyteofeightbitsisfollowedbyoneACKbit.ThetransmittermustreleasetheSDAlinebefore
thereceivercansendanACKbit.ThedevicethatacknowledgesmustpulldowntheSDAlineduringtheACK
clockpulsesothattheSDAlineisstablelowduringthehighpulseoftheACK-relatedclockperiod(see
Figure3).Whenaslavereceiverisaddressed,itmustgenerateanACKaftereachbyteisreceived.Similarly,
themastermustgenerateanACKaftereachbytethatitreceivesfromtheslavetransmitter.Setupandhold
timesmustbemettoensureproperoperation.
Amasterreceiverwillsignalanendofdatatotheslavetransmitterbynotgeneratinganacknowledge(NACK)
afterthelastbytehasbeenclockedoutoftheslave.ThisisdonebythemasterreceiverbyholdingtheSDAline
high.Inthisevent,thetransmittermustreleasethedatalinetoenablethemastertogenerateaStopcondition.
Figure1.DefinitionofStartandStopConditions
Figure2.BitTransfer
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