Datasheet

InterruptOutput(INT)
BusTransactions
Writes
SCL
Start Condition
Data 1 Valid
SDA
Write to Port
Data Out
From Port
R/W ACK From Slave
ACK From Slave
ACK From Slave
1 9
8765432
Data 1
1A20 1
S 11 A1 A0 0 A 0000000 A A P
t
pv
Data to PortCommand ByteSlave Address
SCL
SDA
Data to
Register
Start Condition R/W ACK From Slave ACK From Slave ACK From Slave
1 98765432
Data1/0A20 1S 11 A1 A0 0 A 1000000 A A P
Data to RegisterCommand ByteSlave Address
PCA9554A
www.ti.com ...........................................................................................................................................SCPS127D–SEPTEMBER2006–REVISEDAUGUST2008
Aninterruptisgeneratedbyanyrisingorfallingedgeoftheportinputsintheinputmode.Aftertime,t
iv
,the
signalINTisvalid.Resettingtheinterruptcircuitisachievedwhendataontheportischangedtotheoriginal
setting;dataisreadfromtheportthatgeneratedtheinterruptorinaStopevent.Resettingoccursintheread
modeattheacknowledge(ACK)bitornotacknowledge(NACK)bitaftertherisingedgeoftheSCLsignal.
InterruptsthatoccurduringtheACKorNACKclockpulsecanbelost(orbeveryshort)duetotheresettingof
theinterruptduringthispulse.EachchangeoftheI/OsafterresettingisdetectedandistransmittedasINT.
Readingfromorwritingtoanotherdevicedoesnotaffecttheinterruptcircuit,andapinconfiguredasanoutput
cannotcauseaninterrupt.ChanginganI/Ofromanoutputtoaninputmaycauseafalseinterrupttooccurifthe
stateofthepindoesnotmatchthecontentsoftheInputPortregister.
INThasanopen-drainstructureandrequiresapullupresistortoV
CC
.
DataisexchangedbetweenthemasterandPCA9554Athroughwriteandreadcommands.
DataistransmittedtothePCA9554Abysendingthedeviceaddressandsettingtheleast-significantbittoalogic
0(seeFigure4fordeviceaddress).Thecommandbyteissentaftertheaddressanddetermineswhichregister
receivesthedatathatfollowsthecommandbyte(seeFigure6andFigure7).Thereisnolimitationonthe
numberofdatabytessentinonewritetransmission.
Figure6.WritetoOutputPortRegister
<br/>
Figure7.WritetoConfigurationorPolarityInversionRegisters
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Not Recommended for New Designs