Datasheet

Reads
A20 1S 1
1 A1 A0 0 A A
Data From Register
Slave Address
Slave Address
R/W
ACK From
Slave
Command Byte
ACK From
Slave
S A20
1 11 A1 A0
R/W
1 A Data
A
ACK From
Master
Data
Data From Register
NACK From
Master
NA
P
Last Byte
ACK From
Slave
SCL
SDA
INT
Start
Condition
R/W
Read From
Por
t
Data Into
Port
Stop
Condition
ACK From
Master
NACK From
Master
ACK From
Slave
Data From Port
Slave Address Data From Port
1 9
8765432
A2
0
1S 11 A1 A0
1
A
Data 1 Data 4
A NA
P
Data 2
Data 3 Data 4
t
iv
t
ph
t
ps
t
ir
Data 5
PCA9554A
SCPS127D–SEPTEMBER2006–REVISEDAUGUST2008........................................................................................................................................... www.ti.com
ThebusmasterfirstmustsendthePCA9554Aaddresswiththeleastsignificantbit(LSB)settoalogic0(see
Figure4fordeviceaddress).Thecommandbyteissentaftertheaddressanddetermineswhichregisteris
accessed.Afterarestart,thedeviceaddressissentagain,butthistimetheLSBissettoalogic1.Datafromthe
registerdefinedbythecommandbytethenissentbythePCA9554A(seeFigure8andFigure9).Afterarestart,
thevalueoftheregisterdefinedbythecommandbytematchestheregisterbeingaccessedwhentherestart
occurred.DataisclockedintotheregisterontherisingedgeoftheACKclockpulse.Thereisnolimitationonthe
numberofdatabytesreceivedinonereadtransmission,butwhenthefinalbyteisreceived,thebusmastermust
notacknowledgethedata.
Figure8.ReadFromRegister
<br/>
A.Thisfigureassumesthecommandbytehaspreviouslybeenprogrammedwith00h.
B.TransferofdatacanbestoppedatanymomentbyaStopcondition.
C.Thisfigureeliminatesthecommandbytetransfer,arestart,andslaveaddresscallbetweentheinitialslaveaddress
callandactualdatatransferfromthePport.SeeFigure8forthesedetails.
Figure9.ReadFromInputPortRegister
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Not Recommended for New Designs