Datasheet

www.ti.com
SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for
Acknowledgment
NACK
ACK
PCA9548A
8-CHANNELI
2
CSWITCH
WITHRESET
SCPS143C–OCTOBER2006–REVISEDJUNE2007
Anynumberofdatabytescanbetransferredfromthetransmittertoreceiverbetweenthestartandthestop
conditions.EachbyteofeightbitsisfollowedbyoneACKbit.ThetransmittermustreleasetheSDAlinebefore
thereceivercansendanACKbit.ThedevicethatacknowledgesmustpulldowntheSDAlineduringtheACK
clockpulsesothattheSDAlineisstablelowduringthehighpulseoftheACK-relatedclockperiod(see
Figure3).Whenaslavereceiverisaddressed,itmustgenerateanACKaftereachbyteisreceived.Similarly,
themastermustgenerateanACKaftereachbytethatitreceivesfromtheslavetransmitter.Setupandhold
timesmustbemettoensureproperoperation.
Amasterreceiversignalsanendofdatatotheslavetransmitterbynotgeneratinganacknowledge(NACK)
afterthelastbytehasbeenclockedoutoftheslave.ThisisdonebythemasterreceiverbyholdingtheSDAline
high.Inthisevent,thetransmittermustreleasethedatalinetoenablethemastertogenerateastopcondition.
Figure1.DefinitionofStartandStopConditions
Figure2.BitTransfer
Figure3.AcknowledgmentonI
2
CBus
5
SubmitDocumentationFeedback
Not Recommended For New Designs