Datasheet

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Device Address
1 1 1
0
A10
A0
Slave Address
R/W
Fixed
Hardware
Selectable
Control Register
Interrupt Bits
(Read Only)
Channel-Selection Bits
(Read/Write)
Channel 0
Channel 1
Channel 2
Channel 3
INT0
INT1
INT2
INT3
INT3 INT2 INT1 INT0 B3 B2 B1 B0
7 6
5
4 3 2 1 0
Control Register Definition
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCH
WITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the PCA9545A is shown in Figure 1 . To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Figure 1. PCA9545A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9545A,
which is stored in the control register (see Figure 2 ). If multiple bytes are received by the PCA9545A, it saves
the last byte received. This register can be written and read via the I
2
C bus.
Figure 2. Control Register
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register
(see Table 1 ). After the PCA9545A has been addressed, the control register is written. The four LSBs of the
control byte are used to determine which channel or channels are to be selected. When a channel is selected,
the channel becomes active after a stop condition has been placed on the I
2
C bus. This ensures that all
SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at
the time of connection. A stop condition must occur always right after the acknowledge cycle.
5
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