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SCL
SDA
LEDx
RESET
30%
50%
50%
LED OFF
Start ACK or Read Cycle
t
rst
t
WL
t
REC
t
rst
R
L
= 4.7 kΩ
V
CC
C
L
= 100 pF
(See Note A)
INTERRUPT LOAD CONFIGURATION
DUT
INT
0.5 × V
CC
INTn
(input)
VOLTAGE WAVEFORMS (t
iv
)
t
iv
VOLTAGE WAVEFORMS (t
ir
)
INT
(output)
0.5 × V
CC
INTn
(input)
INT
(output)
0.5 × V
CC
0.5 × V
CC
t
ir
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCH
WITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 11. Reset Timing
A. C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω ,
t
r
/t
f
= 30 ns.
Figure 12. Interrupt Load Circuit and Voltage Waveforms
15
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