Datasheet

www.ti.com
Interrupt and Reset Timing Requirements
PCA9545A
4-CHANNEL I
2
C AND SMBus SWITCH
WITH INTERRUPT LOGIC AND RESET FUNCTIONS
SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12 )
PARAMETER MIN MAX UNIT
t
PWRL
Low-level pulse duration rejection of INTn inputs 1 µ s
t
PWRH
High-level pulse duration rejection of INTn inputs 0.5 µ s
t
WL
Pulse duration, RESET low 6 ns
t
rst
(1)
RESET time (SDA clear) 500 ns
t
REC(STA)
Recovery time from RESET to start 0 ns
(1) t
rst
is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,
signaling a stop condition. It must be a minimum of t
WL
.
13
Submit Documentation Feedback