Datasheet

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Data Output
by Transmitter
SCL From
Master
Start
Condition
S
1 2 8 9
Data Output
by Receiver
Clock Pulse for ACK
NACK
ACK
A AS 1 1 1 0
A2
A1 A0 0
Start Condition
SDA
R/W ACK From Slave ACK From Slave
P
B0B1B2XXXXX
Stop Condition
Slave Address
Control Register
A
NA
S 1 1 1 0
A2
A1 A0 1SDA
INT0INT3 INT2 INT1 P
0
B2 B1 B0
Start Condition R/W ACK From Slave NACK From Master Stop Condition
Slave Address
Control Register
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008
When a slave receiver is addressed, it must generate an acknowledge (ACK) after the reception of each byte.
Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the
SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7 ). Setup and hold times
must be taken into account.
Figure 7. Acknowledgment on the I
2
C Bus
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data is transmitted to the PCA9544A control register using the write mode shown in Figure 8 .
Figure 8. Write Control Register
Data is read from the PCA9544A control register using the read mode shown in Figure 9 .
Figure 9. Read Control Register
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