Datasheet

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SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
SDA
SCL
Start Condition
S
Stop Condition
P
SDA
SCL
Master
Transmitter/
Receiver
Slave
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Master
Transmitter/
Receiver
I
2
C
Multiplexer
Slave
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008
Figure 4. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 5 ).
Figure 5. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master, and the devices that are controlled by the master are the slaves (see
Figure 6 ).
Figure 6. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the
receiver can send an ACK bit.
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