Datasheet
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Power-On Reset
Voltage Translation
2
Maximum
Typical
Minimum
V
CC
(V)
4.543.532.5 5 5.5
1
5
4.5
4
3.5
3
2.5
2
1.5
V
pass
(V)
I
2
C Interface
PCA9544A
4-CHANNEL I
2
C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
SCPS146D – OCTOBER 2005 – REVISED FEBRUARY 2008
When power is applied to V
CC
, an internal power-on reset holds the PCA9544A in a reset condition until V
CC
has
reached V
POR
. At this point, the reset condition is released, and the PCA9544A registers and I
2
C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, V
CC
must
be lowered below 0.2 V to reset the device.
The pass-gate transistors of the PCA9544A are constructed such that the V
CC
voltage can be used to limit the
maximum voltage that is passed from one I
2
C bus to another.
Figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the electrical characteristics section of this data sheet). In order for the PCA9544A to act as a
voltage translator, the V
pass
voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, V
pass
must be equal to or below 2.7 V
to effectively clamp the downstream bus voltages. As shown in Figure 3 , V
pass
(max) is at 2.7 V when the
PCA9544A supply voltage is 3.5 V or lower, so the PCA9544A supply voltage could be set to 3.3 V. Pullup
resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 12 ).
Figure 3. V
pass
Voltage vs V
CC
The I
2
C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 4 ).
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