Datasheet

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S
1 2 8 9
NACK
ACK
DataOutput
byTransmitter
DataOutput
byReceiver
SCL From
Master
Start
Condition
ClockPulsefor
Acknowledgment
SDA
Slave Address
ControlRegister
Stop
Condition
R/W
Start
Condition
Acknowledge
FromSlave
Acknowledge
FromSlave
A1S A0
1
1 1 0 0 0 A A PX X X X X X B1 B0
SDA
Slave Address
ControlRegister
Stop
Condition
R/W
Start
Condition
No Acknowledge
FromMaster
Acknowledge
FromSlave
LastByte
A1S A0
1
1 1 0 0 1 A NA PX X
INT1
INT0
X X B1 B0
PCA9543A
TWO-CHANNEL I
2
C-BUS SWITCH
WITH INTERRUPT LOGIC AND RESET
SCPS169 – SEPTEMBER 2007
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master
must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable
low during the high pulse of the ACK-related clock period (see Figure 8 ). Setup and hold times must be taken
into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Figure 8. Acknowledgment on I
2
C Bus
Data is transmitted to the PCA9543A control register using the write mode shown in Figure 9 .
Figure 9. Write Control Register
Data is read from the PCA9543A control register using the read mode shown in Figure 10 .
Figure 10. Read Control Register
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