Datasheet

1 2
SCL
3 4 5 6 7 8
SDA
A A A
Data 0
R/W
t
pv
9
00 0 0 0 0 0 1
0.7 0.0
Data 11.7
1.0
A
S 1 1 1 0 1 A1 A0 0
t
pv
P
Slave Address
Command Byte Data to Port 0 Data to Port 1
Start Condition
Acknowledge
From Slave
Write to Port
Data Out from Port 1
Data Out from Port 0
Data Valid
Acknowledge
From Slave
Acknowledge
From Slave
PCA9539
SCPS130F –AUGUST 2005–REVISED JANUARY 2011 www.ti.com
RESET Input
A reset can be accomplished by holding the RESET pin low for a minimum of t
W
. The PCA9539 registers and
I
2
C/SMBus state machine are held in their default states until RESET is once again high. This input requires a
pullup resistor to V
CC
, if no active connection is used.
Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t
iv
, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an
interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin
does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to V
CC
.
Bus Transactions
Data is exchanged between the master and PCA9539 through write and read commands.
Writes
Data is transmitted to the PCA9539 by sending the device address and setting the least-significant bit to a logic 0
(see Figure 4 for device address). The command byte is sent after the address and determines which register
receives the data that follows the command byte.
The eight registers within the PCA9539 are configured to operate as four register pairs. The four pairs are Input
Ports, Output Ports, Polarity Inversion ports, and Configuration ports. After sending data to one register, the next
data byte is sent to the other register in the pair (see Figure 6 and Figure 7). For example, if the first byte is sent
to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
Figure 6. Write to Output Port Registers
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