Datasheet

Power-On Reset
RESET Input
Interrupt Output ( INT)
Bus Transactions
Writes
PCA9538
SCPS126E – SEPTEMBER 2006 – REVISED JUNE 2008 ................................................................................................................................................ www.ti.com
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Register 3 (Configuration Register) Table
BIT C7 C6 C5 C4 C3 C2 C1 C0
DEFAULT 1 1 1 1 1 1 1 1
When power (from 0 V) is applied to V
CC
, an internal power-on reset holds the PCA9538 in a reset condition until
V
CC
has reached V
POR
. At that point, the reset condition is released and the PCA9538 registers and SMBus/I
2
C
state machine will initialize to their default states. After that, V
CC
must be lowered to below 0.2 V and then back
up to the operating voltage for a power-reset cycle.
The RESET input can be asserted to reset the system while keeping the V
CC
at its operating level. A reset can
be accomplished by holding the RESET pin low for a minimum of t
W
. The PCA9538 registers and I
2
C/SMBus
state machine are changed to their default states once RESET is low (0). Once RESET is high (1), the I/O levels
at the P port can be changed externally or through the master. This input requires a pullup resistor to V
CC
if no
active connection is used.
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time t
iv
, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting,
data is read from the port that generated the interrupt or in a Stop event. Resetting occurs in the read mode at
the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that
occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt
during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pullup resistor to V
CC
.
Data is exchanged between the master and PCA9538 through write and read commands.
Data is transmitted to the PCA9538 by sending the device address and setting the least-significant bit (LSB) to a
logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte (see Figure 6 and Figure 7 ). There is no limitation on
the number of data bytes sent in one write transmission.
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