Datasheet
Reads
01 0S 00 0 1 0 A A
Data from Register
Slave Address
Slave Address
R/W
ACK From
Slave
Command Byte
ACK From
Slave
S 01 0 00 0 1
R/W
1 A Data
A
ACK From
Master
Data
Data from Register
NACK From Master
NA
P
Last Byte
ACK From
Slave
At this time, the master-transmitter
becomes master-receiver and
slave-receiver becomes
slave-transmitter
SCL
SDA
INT
Start
Condition
R/W
Read From
Port
Data Into
Port
Stop
Condition
ACK From
Master
NACK From
Master
ACK From
Slave
Data From Port
Slave Address Data From Port
1 98765432
0
1
0
S
0
0 0
1
1
A
Data 1 Data 4
A NA
P
Data 2 Data 3 Data 4
t
iv
t
ph
t
ps
t
ir
Data 5
PCA9536
SCPS125F – APRIL 2006 – REVISED AUGUST 2008 .......................................................................................................................................................
www.ti.com
The bus master first must send the PCA9536 address with the LSB set to a logic 0 (see Figure 4 for device
address). The command byte is sent after the address and determines which register is accessed. After a restart,
the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the
command byte then is sent by the PCA9536 (see Figure 8 and Figure 9 ). After a restart, the value of the register
defined by the command byte matches the register being accessed when the restart occurred. Data is clocked
into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes
received in one read transmission, but when the final byte is received, the bus master must not acknowledge the
data.
Figure 8. Read From Register
< br/ >
A. This figure assumes that the command byte previously has been programmed with 00h.
B. Transfer of data can be stopped at any moment by a Stop condition.
C. This figure eliminates the command byte transfer, a restart, and the slave address call between the initial slave
address call and actual data transfer from the P-port (see Figure 8 ).
Figure 9. Read Input Port Register
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