Datasheet

Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Write Polarity
Pulse
Data From
Shift Register
Output Port
Register
Configuration
Register
Input Port
Register
Polarity
Inversion
Register
Polarity
Register Data
Input Port
Register Data
GND
ESD Protection
Diode
P0 to P3
V
CC
Output Port
Register Data
Q1
Q2
D
C
K
FF
Q
Q
D
C
K
FF
Q
Q
D
C
K
FF
Q
Q
D
C
K
FF
Q
Q
100 kW
I/O Port
I
2
C Interface
PCA9536
www.ti.com ....................................................................................................................................................... SCPS125F – APRIL 2006 – REVISED AUGUST 2008
SIMPLIFIED SCHEMATIC OF P0 TO P3
A. At power-on reset, all registers return to default values.
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak
pullup (100 k Ω typ) to V
CC
. The input voltage may be raised above V
CC
to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In
this case, there are low-impedance paths between the I/O pin and either V
CC
or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
The bidirectional I
2
C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I
2
C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 1 ). After the Start condition, the device address byte
is sent, most-significant bit (MSB) first, including the data direction bit (R/ W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse.
On the I
2
C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 2 ).
A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the
master (see Figure 1 ).
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