Datasheet

6
I/O
Port
Shift
Register
4 Bits
Input
Filter
7
Power-On
Reset
Read Pulse
Write Pulse
8
4
GND
V
CC
SDA
SCL
I
2
C Bus
Control
P3−P0
PCA9536
SCPS125F – APRIL 2006 – REVISED AUGUST 2008 ....................................................................................................................................................... www.ti.com
ORDERING INFORMATION
TOP-SIDE
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER
MARKING
(3)
NanoFree™ – WCSP (DSBGA)
Reel of 3000 PCA9536YZPR 7CH
0.23-mm Large Bump – YZP (Pb-free)
PCA9536DR
Reel of 2500
PCA9536DRG4
SOIC – D PCA9536D PD536
– 40 ° C to 85 ° C
Tube of 75
PCA9536DG4
Reel of 250 PCA9536DT
PCA9536DGKR
VSSOP – DGK Reel of 2500 7C_
PCA9536DGKRG4
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging .
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
(3) DGK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
TERMINAL FUNCTIONS
NO. NAME DESCRIPTION
1 P0 P-port input/output. Push-pull design structure.
2 P1 P-port input/output. Push-pull design structure.
3 P2 P-port input/output. Push-pull design structure.
4 GND Ground
5 P3 P-port input/output. Push-pull design structure.
6 SCL Serial clock bus. Connect to V
CC
through a pullup resistor.
7 SDA Serial data bus. Connect to V
CC
through a pullup resistor.
8 V
CC
Supply voltage
LOGIC DIAGRAM
A. All I/Os are set to inputs at reset.
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