Datasheet

SCL
Start Condition
Data 1 Valid
SDA
Write to Port
Data Out
From Port
R/W ACK From Slave
ACK From Slave
ACK From Slave
1 98765432
Data 11A20 1S 00 A1 A0 0 A 0000000 A A P
t
pv
Data to PortCommand ByteSlave Address
Data1/0A20 1S 00 A1 A0 0 A 1000000 A A P
SCL
SDA
Data to
Register
Start Condition R/W ACK From Slave ACK From Slave ACK From Slave
1 98765432
Data to RegisterCommand ByteSlave Address
PCA9534
www.ti.com SCPS124G –SEPTEMBER 2006–REVISED JUNE 2010
Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t
iv
, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an
interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin
does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to V
CC
.
Bus Transactions
Data is exchanged between the master and PCA9534 through write and read commands.
Writes
Data is transmitted to the PCA9534 by sending the device address and setting the least significant bit (LSB) to a
logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte (see Figure 6 and Figure 7). There is no limitation on
the number of data bytes sent in one write transmission.
Figure 6. Write to Output Port Register
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Figure 7. Write to Configuration or Polarity Inversion Registers
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