Datasheet

14
I/O
Port
Shift
Register
8 Bits
LP Filter
Interrupt
Logic
Input
Filter
15
Power-On
Reset
Read Pulse
Write Pulse
2
1
13
16
8
GND
V
CC
SDA
SCL
A1
A0
INT
I
2
C Bus
Control
P7−P0
3
A2
PCA9534
SCPS124G –SEPTEMBER 2006–REVISED JUNE 2010 www.ti.com
Table 2. TERMINAL FUNCTIONS
NO.
SOIC (DW),
NAME DESCRIPTION
SSOP (DB), QFN (RGT
TSSOP (PW), AND AND RGV)
TVSOP (DGV)
1 15 A0 Address input. Connect directly to V
CC
or ground.
2 16 A1 Address input. Connect directly to V
CC
or ground.
3 1 A2 Address input. Connect directly to V
CC
or ground.
4 2 P0 P-port input/output. Push-pull design structure.
5 3 P1 P-port input/output. Push-pull design structure.
6 4 P2 P-port input/output. Push-pull design structure.
7 5 P3 P-port input/output. Push-pull design structure.
8 6 GND Ground
9 7 P4 P-port input/output. Push-pull design structure.
10 8 P5 P-port input/output. Push-pull design structure.
11 9 P6 P-port input/output. Push-pull design structure.
12 10 P7 P-port input/output. Push-pull design structure.
13 11 INT Interrupt output. Connect to V
CC
through a pullup resistor.
14 12 SCL Serial clock bus. Connect to V
CC
through a pullup resistor.
15 13 SDA Serial data bus. Connect to V
CC
through a pullup resistor.
16 14 V
CC
Supply voltage
LOGIC DIAGRAM (POSITIVE LOGIC)
A. Pin numbers shown are for DB, DGV, DW, or PW package.
B. All I/Os are set to inputs at reset.
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