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PCA9518

EXPANDABLE FIVE-CHANNEL I

C HUB

SCPS132A – JUNE 2006 – REVISED JULY 2007

APPLICATION INFORMATION (continued)

The expansion bus signals shown in Figure 4 are included primarily for timing reference points.

All timing on the expansion bus is with respect to 0.5 V

. EXPSDA1 is driven low whenever any SDA pin falls

below 0.3-V V

and EXPSDA2 is driven low when any pin is ≤ 0.4 V. EXPSCL1 is driven LOW whenever any

SCL pin falls below 0.3-V V

and EXPSCL2 is driven LOW when any SCL pin is ≤ 0.4 V. EXPSDA2 returns high

after the SDA pin that was the last one being held below 0.4 V by an external driver starts to rise. The last SDA

to rise above 0.4 V is held down by the PCA9518 to 0.5 V until after the delay of the circuit that determines that

it was the last to rise; then, it is allowed to rise above the 0.5-V level driven by the PCA9518.

Considering the bus 0 SDA to be the last one to go above 0.4 V, then EXPSDA1 returns to high after EXPSDA2

is high and either bus 0 SDA rise time is 1 μ s or bus 0 SDA reaches 0.7-V V

, whichever occurs first. After

both EXPSDA2 and EXPSDA1 are high, the rest of the SDA lines are allowed to rise. The same description

applies to the EXPSCL1, EXPSCL2, and SCL pins.

Any arbitration or clock stretching events on bus 1 requires that the V

of the devices on bus 1 be 70 mV below

the V

of the PCA9518 (see V

– V

ILc

in electrical characteristics) to be recognized by the PCA9518 and then

transmitted to bus 0.

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