Datasheet

www.ti.com
V
OL
OF PCA9518
V
OL
EXPSDA1
EXPSDA2
EXPSCL1
EXPSCL2
BUS n
with n > 1
BUS 0
EXPANSION
BUS
BUS 1
9th Clock Cycle 9th Clock Cycle
t
st
t
ER1
t
r2
t
f2
t
f1
t
r1
V
OL
of Master
V
OL
of PCA9518
SCL of Master
SDA of Master
SCL of Slave
SDA of Slave
t
PLH
of
Slave
t
PLH
PCA9518
EXPANDABLE FIVE-CHANNEL I
2
C HUB
SCPS132A – JUNE 2006 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
If the bus master in Figure 3 were to write to the slave through the PCA9518, the waveform shown in Figure 4
would be created.
Figure 4. Bus Waveforms
Note that any arbitration or clock-stretching events on bus 1 require that the V
OL
of the devices on bus 1 be
70 mV below the V
OL
of the PCA9518 (see V
OL
– V
ILc
in electrical characteristics) to be recognized by the
PCA9518 and transmitted to bus 0.
This looks like a normal I
2
C transmission, except for the small step preceding each clock low-to-high transition
and proceeding each data low-to-high transition for the master. The step height is the difference between the
low level driven by the master and the higher-voltage low level driven by the PCA9518 repeater. Its width
corresponds to an effective clock stretching coming from the PCA9518, which delays the rising edge of the
clock. That same magnitude of delay is seen on the rising edge of the data. The step on the rising edge of the
data is extended through the ninth clock pulse as the PCA9518 repeats the acknowledge from the slave to the
master. The clock of the slave looks normal, except that the V
OL
is the 0.5-V level generated by the PCA9518.
The SDA at the slave has a particularly interesting shape during the ninth clock cycle, when the slave pulls the
line below the value driven by the PCA9518 during the ACK and then returns to the PCA9518 level, creating a
foot before it completes the low-to-high transition. SDA lines, other than the one with the master and the one
with the slave, have a uniform low level driven by the PCA9518 repeater.
11
Submit Documentation Feedback