Datasheet

9th Clock Pulse
V
OL
of PCA9515B
V
OL
of Master
SCL
SDA
I
2
C BUS SLAVE
100 kHz
3.3 V
PCA9515B
5 V
SDA
SCL
I
2
C BUS MASTER
400 kHz
SDA1
SCL1
SDA0
SCL0
EN
SDA
SCL
BUS 0 BUS 1
PCA9515B
www.ti.com SCPS232A –MARCH 2012–REVISED MAY 2013
APPLICATION INFORMATION
A typical application is shown in Figure 2. In this example, the system master is running on a 3.3-V bus, while the
slave is connected to a 5-V bus. Both buses run at 100 kHz, unless the slave bus is isolated. If the slave bus is
isolated, the master bus can run at 400 kHz. Master devices can be placed on either bus.
Figure 2. Typical Application
The PCA9515B is 5.5-V tolerant, so it does not require any additional circuitry to translate between the different
bus voltages.
When one side of the PCA9515B is pulled low by a device on the I
2
C bus, a CMOS hysteresis-type input detects
the falling edge and causes an internal driver on the other side to turn on, thus causing the other side also to go
low. The side driven low by the PCA9515B has a typical value of V
OL
= 0.5 V.
Figure 3 and Figure 4 show the waveforms that are seen in a typical application. If the bus master in Figure 2
writes to the slave through the PCA9515B, Bus 0 has the waveform shown in Figure 3. The waveform looks like
a normal I
2
C transmission until the falling edge of the eighth clock pulse. At that point, the master releases the
data line (SDA) while the slave pulls it low through the PCA9515B. Because the V
OL
of the PCA9515B typically is
around 0.5 V, a step in the SDA is seen. After the master has transmitted the ninth clock pulse, the slave
releases the data line.
Figure 3. Bus 0 Waveforms
Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: PCA9515B