Datasheet

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9th Clock Pulse
V
OL
of PCA9515A
V
OL
of Slave
SCL
SDA
PCA9515A
DUAL BIDIRECTIONAL I
2
C BUS AND SMBus REPEATER
SCPS150B – DECEMBER 2005 – REVISED OCTOBER 2007
Figure 4. Bus 1 Waveforms
On the Bus 1 side of the PCA9515A, the clock and data lines have a positive offset from ground equal to the V
OL
of the PCA9515A. After the eighth clock pulse, the data line is pulled to the V
OL
of the slave device, which is very
close to ground in the example.
It is important to note that any arbitration or clock-stretching events on Bus 1 require that the V
OL
of the devices
on Bus 1 be 70 mV below the V
OL
of the PCA9515A (see V
OL
– V
ILc
in Electrical Characteristics) to be
recognized by the PCA9515A and transmitted to Bus 0.
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