Datasheet

8.0 Registers (Continued)
8.7 INTERRUPT ENABLE REGISTER
This register enables five types of interrupts for the associ-
ated serial channel. Each interrupt can individually activate
the interrupt (INTR) output signal. It is possible to totally
disable the interrupt system by resetting bits 0 through 3 of
the Interrupt Enable Register (IER). Similarly, setting bits of
the IER register to a logic 1, enables the selected inter-
rupt(s). Disabling an interrupt prevents it from being indicat-
ed as active in the IIR and from activating the INTR output
signal. All other system functions operate in their normal
manner, including the setting of the Line Status and
MODEM Status Registers. Table II shows the contents of
the IER. Details on each bit follow:
Bit 0: When set to logic 1 this bit enables the Received Data
Available Interrupt and Timeout Interrupt in the FIFO Mode.
Bit 1: When set to logic 1 this bit enables the Transmitter
Holding Register Empty Interrupt.
Bit 2: When set to logic 1 this bit enables the Receiver Line
Status Interrupt.
Bit 3: When set to logic 1 this bit enables the MODEM
Status Interrupt.
Bits 4 through 7: These four bits are always logic 0.
8.8 MODEM CONTROL REGISTER
This register controls the interface with the MODEM or data
set (or a peripheral device emulating a MODEM). The con-
tents of the MODEM Control Register are indicated in Table
II and are described below:
Bit 0: This bit controls the Data Terminal Ready (DTR
) out-
put. When bit 0 is set to a logic 1, the DTR
output is forced
to a logic 0. When bit 0 is reset to a logic 0, the DTR
output
is forced to a logic 1.
Bit 1: This bit controls the Request to Send (RTS
) output.
Bit 1 affects the RTS
output in a manner identical to that
described above for bit 0.
Bit 2: This bit is the OUT 1
bit. It does not have an output
pin associated with it. It can be written to and read by the
CPU. In Local Loopback Mode this bit controls bit 2 of the
Modem Status Register.
Bit 3: This bit controls the Output 2 (OUT 2
) signal, which is
an auxiliary user-designated output. Bit 3 affects the OUT 2
pin in a manner identical to that described above for bit 0.
The function of this bit is multiplexed on a single output pin
with two other functions: BAUDOUT
and RXRDY. The
OUT 2
function is the default function of the pin after a
master reset. See Section 8.10 for more information about
selecting one of these 3 pin functions.
Bit 4: This bit provides a local loopback feature for diagnos-
tic testing of the associated serial channel. When bit 4 is set
to logic 1, the following occur: the transmitter Serial Output
(SOUT) is set to the Marking (logic 1) state; the receiver
Serial Input (SIN) is disconnected; the output of the Trans-
mitter Shift Register is ‘‘looped back’’ into the Receiver Shift
Register input; the four MODEM Control inputs (DSR
, CTS,
RI
, and DCD) are disconnected; the four MODEM Control
outputs (DTR
, RTS, OUT 1, and OUT 2) are internally con-
nected to the four MODEM Control inputs; and the MODEM
Control output pins are forced to their inactive state (high).
In this diagnostic mode, data that is transmitted is immedi-
ately received. This feature allows the processor to verify
transmit and receive data paths of the DUART.
In this diagnostic mode, the receiver and transmitter inter-
rupts are fully operational. Their sources are external to the
part. The MODEM Control Interrupts are also operational,
but the interrupts’ sources are now the lower four bits of the
MODEM Control Register instead of the four MODEM Con-
trol inputs. The interrupts are still controlled by the Interrupt
Enable Register.
Bits 5 through 7: These bits are permanently set to logic 0.
8.9 MODEM STATUS REGISTER
This register provides the current state of the control lines
from the MODEM (or peripheral device) to the CPU. In addi-
tion to this current-state information, four bits of the
MODEM Status Register provide change information. The
latter bits are set to a logic 1 whenever a control input from
the MODEM changes state. They are reset to logic 0 when-
ever the CPU reads the MODEM Status Register.
The contents of the MODEM Status Register are indicated
in Table II and described below.
Bit 0: This bit is the Delta Clear to Send (DCTS) indicator.
Bit 0 indicates that the CTS
input to the chip has changed
state since the last time it was read by the CPU.
Bit 1: This bit is the Delta Data Set Ready (DDSR) indicator.
Bit 1 indicates that the DSR
input to the chip has changed
state since the last time it was read by the CPU.
Bit 2: This bit is the Trailing Edge of Ring Indicator (TERI)
detector. Bit 2 indicates that the RI
input to the chip has
changed from a low to a high state.
Bit 3: This bit is the Delta Data Carrier Detect (DDCD) indi-
cator. Bit 3 indicates that the DCD
input to the chip has
changed state.
Note: Whenever bit 0, 1, 2, or 3 is set to logic 1, a MODEM Status Interrupt
is generated.
Bit 4: This bit is the complement of the Clear to Send (CTS)
input. If bit 4 (loop) of the MCR is set to a 1, this bit is
equivalent to RTS in the MCR.
Bit 5: This bit is the complement of the Data Set Ready
(DSR
) input. If bit 4 of the MCR is set to a 1, this bit is
equivalent to DTR in the MCR.
Bit 6: This bit is the complement of the Ring Indicator (RI
)
input. If bit 4 of the MCR is set to a 1, this bit is equivalent to
OUT 1 in the MCR.
Bit 7: This bit is the complement of the Data Carrier Detect
(DCD
) input. If bit 4 of the MCR is set to a 1, this bit is
equivalent to OUT 2 in the MCR.
8.10 ALTERNATE FUNCTION REGISTER
This is a read/write register used to select specific modes of
operation. It is located at address 010 when the DLAB bit is
set.
Bit 0: When this bit is set the CPU can write concurrently to
the same register in both register sets. This function is in-
tended to reduce the DUART initialization time. It can be
used by a CPU when both channels are initialized to the
same state. The CPU can set or clear this bit by accessing
either register set. When this bit is set the channel select pin
still selects the channel to be accessed during read opera-
tions. Setting or clearing this bit has no effect on read oper-
ations.
The user should ensure that the DLAB bit (LCR7) of both
channels are in the same state before executing a concur-
rent write to register addresses 0, 1 and 2.
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