Datasheet

8.0 Registers (Continued)
Bit 4: This bit is the Break Interrupt (BI) indicator. Bit 4 is set
to a logic 1 whenever the received data input is held in the
Spacing (logic 0) state for longer than a full word transmis-
sion time (that is, the total time of Start bit
a
data bits
a
Parity
a
Stop bits). The BI indicator is reset whenever the
CPU reads the contents of the Line Status Register or when
the next valid character is loaded into the Receiver Buffer
Register. In the FIFO Mode this condition is associated with
the particular character in the FIFO it applies to. It is re-
vealed to the CPU when its associated character is at the
top of the FIFO. When break occurs only one zero character
is loaded into the FIFO. The next character transfer is en-
abled after SIN goes to the marking state and receives the
next valid start bit.
Note: Bits 1 through 4 are the error conditions that produce a Receiver Line
Status interrupt whenever any of the corresponding conditions are
detected and the interrupt is enabled.
Bit 5: This bit is the Transmitter Holding Register Empty
(THRE) indicator. In the 16450 mode bit 5 indicates that the
associated serial channel is ready to accept a new charac-
ter for transmission. In addition, this bit causes the DUART
to issue an interrupt to the CPU when the Transmit Holding
Register Empty Interrupt enable is set high. The THRE bit is
set to a logic 1 when a character is transferred from the
Transmitter Holding Register into the Transmitter Shift Reg-
ister. The bit is reset to logic 0 concurrently with the loading
of the Transmitter Holding Register by the CPU. In the FIFO
mode this bit is set when the XMIT FIFO is empty; it is
cleared when at least 1 byte is written to the XMIT FIFO.
Bit 6: This bit is the Transmitter Empty (TEMT) indicator. Bit
6 is set to a logic 1 whenever the Transmitter Holding Regis-
ter (THR) and the Transmitter Shift Register (TSR) are both
empty. It is reset to a logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is
set to one whenever the transmitter FIFO and shift register
are both empty.
Bit 7: In the 16450 Mode this is a 0. In the FIFO Mode LSR7
is set when there is at least one parity error, framing error or
break indication in the FIFO. LSR7 is cleared when the CPU
reads the LSR, if there are no subsequent errors in the
FIFO.
Note: The Line Status Register is intended for read operations only. Writing
to this register is not recommended as this operation is only used for
factory testing. In the FIFO mode the user must load a data byte into
the Rx FIFO in order to write to LSR2–4. LSR0 and LSR7 cannot be
written to in the FIFO mode.
8.5 FIFO CONTROL REGISTER
This is a write only register at the same location as the IIR
(the IIR is a read only register). This register is used to en-
able the FIFOs, clear the FIFOs, set the RCVR FIFO trigger
level, and select the type of DMA signalling.
Bit 0: Writinga1toFCR0 enables both the XMIT and RCVR
FIFOs. Resetting FCR0 will clear all bytes in both FIFOs.
When changing from FIFO Mode to 16450 Mode and vice
versa, data is automatically cleared from the FIFOs. This bit
must be a 1 when other FCR bits are written to or they will
not be programmed.
Bit 1: Writinga1toFCR1 clears all bytes in the RCVR FIFO
and resets its counter logic to 0. The shift register is not
cleared. The 1 that is written to this bit position is self-clear-
ing.
Bit 2: Writinga1toFCR2 clears all bytes in the XMIT FIFO
and resets its counter logic to 0. The shift register is not
cleared. The 1 that is written to this bit position is self-clear-
ing.
Bit 3: Writinga1toFCR3 causes RXRDY
and TXRDY oper-
ations to change from mode 0 to mode 1 if FCR0
e
1.
RXRDY Mode 0: When in the 16450 Mode (FCR0
e
0) or
in the FIFO Mode (FCR0
e
1, FCR3
e
0) and there is at
least 1 character in the RCVR FIFO or RCVR Buffer Regis-
ter, the RXRDY
pin will go low active. Once active the
RXRDY
pin will go inactive when there are no more charac-
ters in the FIFO or Buffer Register.
TABLE IV. Baud Rates, Divisors and Crystals
1.8432 MHz Crystal 3.072 MHz Crystal 18.432 MHz Crystal
Baud Rate
Decimal Divisor
Percent Error
Decimal Divisor
Percent Error
Decimal Divisor
Percent Error
for 16
c
Clock for 16
c
Clock for 16
c
Clock
50 2304 Ð 3840 Ð 23040 Ð
75 1536 Ð 2560 Ð 15360 Ð
110 1047 0.026 1745 0.026 10473 Ð
134.5 857 0.058 1428 0.034 8565 Ð
150 768 Ð 1280 Ð 7680 Ð
300 384 Ð 640 Ð 3840 Ð
600 192 Ð 320 Ð 1920 Ð
1200 96 Ð 160 Ð 920 Ð
1800 64 Ð 107 0.312 640 Ð
2000 58 0.69 96 Ð 576 Ð
2400 48 Ð 80 Ð 480 Ð
3600 32 Ð 53 0.628 320 Ð
4800 24 Ð 40 Ð 240 Ð
7200 16 Ð 27 1.23 160 Ð
9600 12 Ð 20 Ð 120 Ð
19200 6 Ð 10 Ð 60 Ð
38400 3 Ð 5 Ð 30 Ð
56000 2 2.86 Ð Ð 21 2.04
128000 Ð Ð Ð Ð 9 Ð
Note: For baud rates of 250k, 300k, 375k, 500k, 750k and 1.5M using a 24 MHz crystal causes minimal error.
17