Datasheet

TABLE II. Register Summary for an Individual Channel
Register Address
0 DLAB
e
0 0 DLAB
e
0 1 DLAB
e
0 2 2 3 4 5 6 7 0 DLAB
e
1 1 DLAB
e
1 2 DLAB
e
1
Receiver Transmitter Interrupt FIFO
Bit Buffer Holding Interrupt Ident. Control Line MODEM Line MODEM Scratch Divisor Divisor Alternate
No. Register Register Enable Register Register Control Control Status Status Reg- Latch Latch Function
(Read (Write Register (Read (Write Register Register Register Register ister (LS) (MS) Register
Only) Only) Only) Only)
RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM AFR
0 Data Bit 0 Data Bit 0 Enable ‘‘0’’ if FIFO Word Data Data Delta Bit 0 Bit 0 Bit 8 Concurrent
(Note 1) Received Interrupt Enable Length Terminal Ready Clear Write
Data Pending Select Ready (DR) to Send
Available Bit 0 (DTR) (DCTS)
Interrupt (WLS0)
(ERDAI)
1 Data Bit 1 Data Bit 1 Enable Interrupt RCVR Word Request Overrun Delta Bit 1 Bit 1 Bit 9 BAUDOUT
Transmitter ID FIFO Length to Send Error Data Select
Holding Bit Reset Select (RTS) (OE) Set
Register Bit 1 Ready
Empty (WLS1) (DDSR)
Interrupt
(ETHREI)
2 Data Bit 2 Data Bit 2 Enable Interrupt XMIT Number of Out 1 Parity Trailing Bit 2 Bit 2 Bit 10 RXRDY
Receiver ID FIFO Stop Bits (Note 3) Error Edge Ring Select
Line Status Bit Reset (STB) (PE) Indicator
Interrupt (TERI)
(ELSI)
3 Data Bit 3 Data Bit 3 Enable Interrupt DMA Parity Out 2 Framing Delta Bit 3 Bit 3 Bit 11 0
MODEM ID Mode Enable Error Data
Status Bit Select (PEN) (FE) Carrier
Interrupt (Note 2) Detect
(EMSI) (DDCD)
4 Data Bit 4 Data Bit 4 0 0 Reserved Even Loop Break Clear Bit 4 Bit 4 Bit 12 0
Parity Interrupt to
Select (BI) Send
(EPS) (CTS)
5 Data Bit 5 Data Bit 5 0 0 Reserved Stick 0 Transmitter Data Bit 5 Bit 5 Bit 13 0
Parity Holding Set
Register Ready
(THRE) (DSR)
6 Data Bit 6 Data Bit 6 0 FIFOs RCVR Set 0 Transmitter Ring Bit 6 Bit 6 Bit 14 0
Enabled Trigger Break Empty Indicator
(Note 2) (LSB) (TEMT) (RI)
7 Data Bit 7 Data Bit 7 0 FIFOs RCVR Divisor 0 Error in Data Bit 7 Bit 7 Bit 15 0
Enabled Trigger Latch RCVR Carrier
(Note 2) (MSB) Access Bit FIFO Detect
(DLAB) (Note 2) (DCD)
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received. Note 2: These bits are always 0 in the 16450 Mode. Note 3: This bit no longer has a pin associated with it.
14