Datasheet
3.0 AC Electrical Characteristics T
A
e
0
§
Cto
a
70
§
C, V
DD
ea
5V
g
10%
Symbol Parameter Conditions Min Max Units
t
AR
RD Delay from Address 15 ns
t
AW
WR Delay from Address 15 ns
t
DH
Data Hold Time 5 ns
t
DS
Data Setup Time 15 ns
t
HZ
RD to Floating Data Delay (Note 2) 10 20 ns
t
MR
Master Reset Pulse Width 500 ns
t
RA
Address Hold Time from RD 0ns
t
RC
Read Cycle Update 29 ns
t
RD
RD Strobe Width 40 ns
t
RVD
Delay from RD to Data 25 ns
t
WA
Address Hold Time from WR 0ns
t
WC
Write Cycle Update 29 ns
t
WR
WR Strobe Width 40 ns
t
XH
Duration of Clock High Pulse External Clock (24 MHz Max) 17 ns
t
XL
Duration of Clock Low Pulse External Clock (24 MHz Max) 17 ns
RC Read Cycle
e
t
AR
a
t
RD
a
t
RC
84 ns
WC Write Cycle
e
t
AW
a
t
WR
a
t
WC
84 ns
BAUD GENERATOR
N Baud Divisor 1 2
16
b
1
t
BHD
Baud Output Positive Edge Delay f
X
e
24 MHz,
d
245ns
t
BLD
Baud Output Negative Edge Delay f
X
e
24 MHz,
d
245ns
RECEIVER
t
RAI
Delay from Active Edge of RD to
78 ns
Reset Interrupt
t
RINT
Delay from Inactive Edge of RD
(RD LSR) 40 ns
to Reset Interrupt
t
RXI
Delay from READ to RXRDY Inactive 55 ns
t
SCD
Delay from RCLK to Sample Time 33 ns
t
SINT
Delay from Stop to Set Interrupt (Note 1)
2
BAUDOUT
Cycles
Note 1: In the FIFO mode (FCR0
e
1) the trigger level interrupts, the receiver data available indication, the active RXRDY indication and the overrun error
indication will be delayed 3 RCLKs. Status indicators (PE, FE, BI) will be delayed 3 RCLKs after the first byte has been received. For subsequently received bytes
these indicators will be updated immediately after RDRBR goes inactive. Timeout interrupt is delayed 8 RCLKs.
Note 2: Charge and discharge time is determined by V
OL
,V
OH
and the external loading.
Note 3: All AC timings can be met with current loads that don’t exceed 3.2 mA or
b
80 mA at 100 pF capacitive loading.
Note 4: For capacitive loads that exceed 100 pF the following typical derating factors should be used:
100 pF
k
C
L
s
150 pF t
e
(0.1 ns/pF)(C
L
b
100 pF)
150 pF
k
C
L
s
200 pF t
e
(0.08 ns/pF)(C
L
b
100 pF)
I
SINK
t
e
(0.5 ns/mA)(I
SINK
mA)
I
SOURCE
t
e
(0.5 ns/mA)(I
SOURCE
mA)
Limits: I
SOURCE
is negative, I
SINK
s
4.8 mA, I
SOURCE
s
b
120 mA, C
L
s
250 pF
AC Testing Load Circuit
TL/C/9426–22
4