Datasheet
3.0 AC Electrical Characteristics T
A
e
0
§
Cto
a
70
§
C, V
DD
ea
5V
g
10%
Symbol Parameter Conditions Min Max Units
t
ADS
Address Strobe Width 60 ns
t
AH
Address Hold Time 0 ns
t
AR
RD, RD Delay from Address (Note 1) 30 ns
t
AS
Address Setup Time 60 ns
t
AW
WR, WR Delay from Address (Note 1) 30 ns
t
CH
Chip Select Hold Time 0 ns
t
CS
Chip Select Setup Time 60 ns
t
CSR
RD, RD Delay from Chip Select (Note 1) 30 ns
t
CSW
WR, WR Delay from Select (Note 1) 30 ns
t
DH
Data Hold Time 30 ns
t
DS
Data Setup Time 30 ns
t
HZ
RD, RD to Floating Data Delay
@
100 pF loading (Note 3) 0 100 ns
t
MR
Master Reset Pulse Width 5000 ns
t
RA
Address Hold Time from RD, RD (Note 1) 20 ns
t
RC
Read Cycle Delay 125 ns
t
RCS
Chip Select Hold Time from RD, RD (Note 1) 20 ns
t
RD
RD, RD Strobe Width 125 ns
t
RDD
RD, RD to Driver Enable/Disable
@
100 pF loading (Note 3) 60 ns
t
RVD
Delay from RD, RD to Data
@
100 pF loading 60 ns
t
WA
Address Hold Time from WR, WR (Note 1) 20 ns
t
WC
Write Cycle Delay 150 ns
t
WCS
Chip Select Hold Time from WR, WR (Note 1) 20 ns
t
WR
WR, WR Strobe Width 100 ns
t
XH
Duration of Clock High Pulse External Clock (8, Max.) 55 ns
t
XL
Duration of Clock Low Pulse External Clock (8, Max.) 55 ns
RC Read Cycle
e
t
AR
a
t
RD
a
t
RC
280 ns
WC Write Cycle
e
t
AW
a
t
WR
a
t
WC
280 ns
Baud Generator
N Baud Divisor 1 2
16
b
1
t
BHD
Baud Output Positive Edge Delay 100 pF Load 175 ns
t
BLD
Baud Output Negative Edge Delay 100 pF Load 175 ns
t
HW
Baud Output Up Time f
X
e
8,
d
2, 100 pF Load 75 ns
t
LW
Baud Output Down Time f
X
e
8,
d
2, 100 pF Load 100 ns
Receiver
t
RAI
Delay from Active Edge
Ðns
of RD
to Reset Interrupt
t
RINT
Delay from RD, RD 100 pF Load
(RD RBR/or RD LSR) 1000 ns
to Reset Interrupt
t
RXI
Delay from RD RBR
290 ns
to RXRDY
Inactive
t
SCD
Delay from RCLK to Sample Time 2000 ns
t
SINT
Delay from Stop to Set Interrupt (Note 2)
1
RCLK
Cycles
Note 1: Applicable only when ADS is tied low.
Note 2: In the FIFO mode (FCR0
e
1) the trigger level interrupts, the receiver data available indication, the active RXRDY indication and the overrun error indication
will be delayed 3 RCLKs. Status indicators (PE, FE, BI) will be delayed 3 RCLKs after the first byte has been received. For subsequently received bytes these
indicators will be updated immediately after RDRBR goes inactive. Timeout interrupt is delayed 8 RCLKs.
Note 3: Charge and discharge time is determined by V
OL
,V
OH
and the external loading.
Note 4: These specifications are preliminary.
4