Datasheet

7.0 Connection Diagrams (Continued)
TQFP Package
TL/C/8652–26
Order Number PC16550DVEF
See NS Package Number VEF44A
Chip Carrier Package
TL/C/8652–18
Top View
Order Number PC16550DV
See NS Package Number V44A
TABLE I. UART Reset Configuration
Register/Signal Reset Control Reset State
Interrupt Enable Register Master Reset 0000 0000 (Note 1)
Interrupt Identification Register Master Reset 0000 0001
FIFO Control Master Reset 0000 0000
Line Control Register Master Reset 0000 0000
MODEM Control Register Master Reset 0000 0000
Line Status Register Master Reset 0110 0000
MODEM Status Register Master Reset XXXX 0000 (Note 2)
SOUT Master Reset High
INTR (RCVR Errs) Read LSR/MR Low
INTR (RCVR Data Ready) Read RBR/MR Low
INTR (THRE) Read IIR/Write THR/MR Low
INTR (Modem Status Changes) Read MSR/MR Low
OUT 2 Master Reset High
RTS Master Reset High
DTR Master Reset High
OUT 1 Master Reset High
RCVR FIFO MR/FCR1
#
FCR0/DFCR0 All Bits Low
XMIT FIFO MR/FCR1
#
FCR0/DFCR0 All Bits Low
Note 1: Boldface bits are permanently low.
Note 2: Bits 7 – 4 are driven by the input signals.
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