Datasheet

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Electrical Characteristics
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
V
CC
= 2.3 V to 2.7 V, voltages are specified with respect to GND (unless otherwise noted)
T
A
= 25 ° C T
A
= –40 ° C to 85 ° C
TEST
PARAMETER UNIT
CONDITIONS
MIN TYP
(1)
MAX MIN MAX
Temperature coefficient of
Δ V/ Δ T
IN
Sx, Sy –2 mV/ ° C
input thresholds
I
Sx
, I
Sy
= 3 mA 0.8 0.88 1
V
OL
Low-level output voltage Sx, Sy
(2)
V
I
Sx
, I
Sy
= 0.2 mA 0.67 0.73 0.79
(2)
Temperature coefficient of
Δ V/ Δ T
OUT
Sx, Sy I
Sx
, I
Sy
= 0.2 mA –1.8 mV/ ° C
output low levels
(3)
I
CC
Quiescent supply current Sx = Sy = V
CC
0.9 1.8 2 mA
Additional supply current
Δ I
CC
Tx, Ty 1.7 2.75 3 mA
per pin low
Dynamic output sink V
Sx
, V
Sy
> 2 V,
7 18 5.5 mA
capability on I
2
C bus V
Rx
, V
Ry
= low
I
IOS
Sx, Sy
V
Sx
, V
Sy
= 2.5 V,
Leakage current on I
2
C bus 0.1 1 1 μ A
V
Rx
, V
Ry
= high
V
Tx
, V
Ty
> 1 V,
Dynamic output sink
Tx, Ty V
Sx
, V
Sy
= low on 60 100 60 mA
capability on buffered bus
I
2
C bus = 0.4 V
I
IOT
V
Tx
, V
Ty
= V
CC
=
Leakage current
2.5 V, 0.1 1 1 μ A
on buffered bus
V
Sx
, V
Sy
= high
Bus low, V
Rx
,
Input current from I
2
C bus Sx, Sy –1 1
V
Ry
= high
Input current Bus low, V
Rx
,
I
I
–1 1 μ A
from buffered bus V
Ry
= 0.4 V
Rx, Ry
Leakage current
V
Rx
, V
Ry
= V
CC
1 1.5
on buffered bus input
Input logic level high
threshold
(4)
0.65 0.7
(2)
on normal I
2
C bus
Sx, Sy
Input logic level low
threshold
(4)
0.6 0.65
(2)
V
IT
Input threshold V
on normal I
2
C bus
Input logic level high 0.58 V
CC
0.58 V
CC
Rx, Ry Input threshold 0.5 V
CC
Input logic level low 0.42 V
CC
0.42 V
CC
(V
Sx
output low
Input/output logic level at 3 mA) –
V
IOdiff
Sx, Sy 100 150 100 mV
difference
(5)
(V
Sx
input high max)
for I
2
C applications
Sx, Sy are low, V
CC
V
CC
voltage at which all Sx, Sy ramping, voltage on
V
IOrel
1 1 V
buses are released Tx, Ty Tx, Ty lowered until
released
Temperature coefficient of release
Δ V/ Δ T
REL
–4 mV/ ° C
voltage
C
in
Input capacitance Rx, Ry 2.5 4 4 pF
(1) Typical value is at V
CC
= 2.5 V, T
A
= 25 ° C
(2) See the Typical Characteristics section of this data sheet.
(3) The output logic low depends on the sink current.
(4) The input logic threshold is independent of the supply voltage.
(5) The minimum value requirement for pullup current, 200 μ A, ensures that the minimum value for V
SX
output low always exceeds the
minimum V
Sx
input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications. In any design, the Sx pins of different devices should never be linked,
because the resulting system would be very susceptible to induced noise and would not support all I
2
C operating modes.
5
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