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Sample Calculations
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
The master bus has an RmCm product of 100 ns and V
CCM
= 5 V.
The buffered bus has a capacitance of 1 nF and a pullup resistor of 160 Ω to 5 V, giving an RbCb product of
160 ns. The slave bus also has an RsCs product of 100 ns.
The master low period should be programmed to be ≥ (1300 + 372.5 – 482 + 472) ns, which calculates to
≥ 1662.5 ns.
The master high period may be programmed to the minimum 600 ns. The nominal master clock period is
≥ (1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of 442 kHz.
The actual bus-clock period, including the 482-ns clock stretch effect, is below
(nominal + stretch) = (2262.5 + 482) ns or ≥ 2745 ns, equivalent to an allowable frequency of 364 kHz.
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