Datasheet

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MASTER
P82B96 P82B96
SDA
Rm
Rb
Rs
SDA
Sx
Tx/Rx
Tx/Rx
Sx
GND
I C
2
V
CCS
Local Master Bus
V
CCM
Cb=BufferedBus
WiringCapacitance
Cm=MasterBus
Capacitance
Cs=SlaveBus
Capacitance
BufferedExpansionBus
RemoteSlaveBus
I C
2
SLAVE
V
CCB
RisingedgeofSDA atslaveisdelayedbythebuffersandbusrisetimes.
EffectivedelayofSDA atmaster=270+0.2RsCs+0.7(RbCb+RmCm)(ns)
C=F,R= Ω
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
Figure 9.
The delay factors involved in calculation of the allowed bus speed are:
1. The propagation delay of the master signal through the buffers and wiring to the slave. The important
delay is that of the falling edge of SCL, because this edge requests the data or ACK from a slave.
2. The effective stretching of the nominal low period of SCL at the master, caused by the buffer and bus rise
times.
3. The propagation delay of the slave response signal through the buffers and wiring back to the master.
The important delay is that of a rising edge in the SDA signal. Rising edges always are slower and,
therefore, are delayed by a longer time than falling edges. (The rising edges are limited by the passive
pullup, while falling edges actively are driven.)
The timing requirement in any I
2
C system is that a slave’s data response (which is provided in response to a
falling edge of SCL) must be received at the master before the end of the corresponding low period of SCL as it
appears on the bus wiring at the master. Because all slaves, as a minimum, satisfy the worst-case timing
requirements of a 400-kHz part, they must provide their response within the minimum allowed clock low period
of 1300 ns. Therefore, in systems that introduce additional delays, it is necessary only to extend that minimum
clock low period by any effective delay of the slave response. The effective delay of the slave's response equals
the total delays in SCL falling edge from the master reaching the slave (A) minus the effective delay (stretch) of
the SCL rising edge (B) plus total delays in the slave response data, carried on SDA, and reaching the master
(C).
The master microcontroller should be programmed to produce a nominal SCL low period
of (1300 + A – B + C) ns and should be programmed to produce the nominal minimum SCL high period of
600 ns. Then, a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. If
found to be necessary, increase either clock period.
Due to clock stretching, the SCL cycle time always is longer than (600 + 1300 + A + C) ns.
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