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Calculating System Delays and Bus-Clock Frequency for Fast Mode System
MASTER
I C
2
I C
2
SLAVE
P82B96
P82B96
SCL
Rm
Rb Rs
V
CCS
SCL
Sx
Tx/Rx
Tx/Rx
Sx
GND
Falling edge of SCL at master is delayed by the buffers and bus fall times.
Local Master Bus
V
CCB
EffectiveDelayofSCL atSlave=255+17V +(2.5+4 10 Cb)V (ns)
C=F,V=Volts
CCM CCB
×
9
V
CCM
Cb=BufferedBus
WiringCapacitance
Cm=MasterBus
Capacitance
Cs=SlaveBus
Capacitance
BufferedExpansionBus
RemoteSlaveBus
MASTER
P82B96
V
CCM
SCL
Rm
Rb
Sx
Tx/Rx
Tx/Rx
GND
V
CCB
I C
2
Cb=BufferedBus
WiringCapacitance
Cm=MasterBus
Capacitance
RisingedgeofSCL atmasterisdelayed(clockstretch)bybufferandbusrisetimes.
EffectivedelayofSCL atmaster=270+RmCm+0.7RbCb(ns)
C=F,R= Ω
LocalMasterBus
BufferedExpansionBus
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
Note that, in both the 100-m and 250-m examples, the capacitive loading on the I
2
C buses at each end is within
the maximum allowed Standard mode loading of 400 pF, but exceeds the Fast mode limit. This is an example of
a hybrid mode, because it relies on the response delays of Fast mode parts, but uses (allowable) Standard
mode bus loadings with rise times that contribute significantly to the system delays. The cables cause large
propagation delays. Therefore, these systems must operate well below the 400-kHz limit, but illustrate how they
still can exceed the 100-kHz limit, provided all parts are capable of Fast mode operation. The fastest example
illustrates how the 400-kHz limit can be exceeded, provided master and slave parts have delay specifications
smaller than the maximum allowed. Many TI slaves have delays shorter than 600 ns, but none have that
specified.
Figure 7 through Figure 9 show the P82B96 used to drive extended bus wiring, with relatively large capacitance,
linking two Fast mode I
2
C bus nodes. It includes simplified expressions for making the relevant timing
calculations for 3.3-/5-V operation. Because the buffers and the wiring introduce timing delays, it may be
necessary to decrease the nominal SCL frequency below 400 kHz. In most cases, the actual bus frequency is
lower than the nominal master timing, due to bit-wise stretching of the clock periods.
Figure 7.
Figure 8.
17
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