Datasheet

www.ti.com
SCL
SDA
P82B96
GND
SCL
SDA
P82B96
R1R1
R2R2
R2 R2
R1
R1
Cable
+V Cable Drive
Propagation
Delay = 5 ns/m
I C
MASTER
2
I C
SLAVE(S)
2
C2 C2
V
CC1
V
CC
Rx
Tx
Ry
Ty
Sx
Sy
V
CC
Rx
Tx
Ry
Ty
Sx
Sy
V
CC2
GND
BAT54A BAT54A
C2 C2
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
end, it is crossed after two times the one-way propagation delay and, at the receiving end, after three times that
propagation delay. For flat cables with partial plastic dielectric insulation (by using outer cores) the one-way
propagation delays are about 5 ns/m. The 10% to 90% rise and fall times on the cable are between 20 ns and
50 ns, so their delay contributions are small. There is ringing on falling edges that can be damped, if required,
using Schottky diodes, as shown.
Figure 6. Driving Ribbon or Flat Telephone Cables
Table 1. Bus Capabilities
MASTER SCL
BUS MAXIMUM
PULSE
+V CABLE CABLE
V
CC1
V
CC2
R1 R2 C2 CABLE CLOCK SLAVE
DURATION
CABLE LENGTH DELAY
(V) (V) ( Ω ) (k Ω ) (pF) CAPACITANCE SPEED RESPONSE
(ns)
(V) (m) (ns)
(kHz) DELAY
HIGH LOW
5 12 5 750 2.2 400 250
(1)
1250 600 4000 120
(2)
5 12 5 750 2.2 220 100
(1)
500 600 2600 185
(2)
3.3 5 3.3 330 1 220 25 1 nF 125 600 1500 390
(2)
3.3 5 3.3 330 1 100 3 120 pF 15 600 1000 500 600 ns
(1) Not applicable; calculations are delay based.
(2) Normal 400-kHz bus specification
When the master SCL high and low periods can be programmed separately, the timings can allow for bus
delays. The low period should be programmed to achieve the minimum 1300 ns plus the net delay in the slave
response data signal caused by bus and buffer delays. The longest data delay is the sum of the delay of the
falling edge of SCL from master to slave and the delay of the rising edge of SDA from slave data to master.
Because the buffer stretches the programmed SCL low period, the actual SCL frequency is lower than
calculated from the programmed clock periods. In the example for the 25-m cable in Table 1 , the clock is
stretched 400 ns, the falling edge of SCL is delayed 490 ns, and the SDA rising edge is delayed 570 ns. The
required additional low period is (490 + 570) = 1060 ns and the I
2
C bus specifications already include an
allowance for a worst-case bus rise time (0% to 70%) of 425 ns. The bus rise time can be 300 ns (30% to 70%),
which means it can be 425 ns (0% to 70%). The 25-m cable delay times include all rise and fall times.
Therefore, the device only needs to be programmed with an additional (1060 – 400 – 425) = 235 ns, making a
total programmed low period 1535 ns. The programmed low is stretched by 400 ns to yield an actual bus low
time of 1935 ns, which, allowing the minimum high period of 600 ns, yields a cycle period of 2535 ns or 394 kHz.
16
Submit Documentation Feedback