Datasheet

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SCL
SCL
SDA
P82B96
3-m to 20-m Cables
P82B96
V
+V Cable Drive
V
CC
I C/DDC
2
Master
GND
Sx
Sy
Rx
Tx
Ry
Ty
470 kW
4700 W
I C/DDC
2
Rx
Tx
Ty
Ry
V
CC1
V
CC2
Sx
Sy
I C/DDC
2
Slave
PC/TV Receiver/Decoder Box
Monitor/Flat TV
Video Signals
R
G
B
100 k
W
100 nF
470 kW
+V Cable Drive
V
CC
GND
BC
847B
BC
847B
SDA
P82B96
DUAL BIDIRECTIONAL BUS BUFFER
SCPS144B – MAY 2006 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
Figure 5 shows how a master I
2
C bus can be protected against short circuits or failures in applications that
involve plug/socket connections and long cables that may become damaged. A simple circuit is added to
monitor the SDA bus and, if its low time exceeds the design value, disconnect the master bus. P82B96 frees all
of its I/Os if its supply is removed, so one option is to connect its V
CC
to the output of a logic gate from, for
example, the LVC family. The SDA and SCL lines could be timed, and V
CC
disabled via the gate, if a line
exceeds a design value of the low period. If the supply voltage of logic gates restricts the choice of V
CC
supply,
the low-cost discrete circuit in Figure 5 can be used. If the SDA line is held low, the 100-nF capacitor charges,
and Ry is pulled toward V
CC
. When it exceeds V
CC
/2, Ry sets Sy high, which effectively releases it.
Figure 5. Extending DCC Bus
In this example, the SCL line is made unidirectional by tying Rx to V
CC
. The state of the buffered SCL line
cannot affect the master clock line, which is allowed when clock stretching is not required. It is simple to add an
additional transistor or diode to control the Rx input in the same way as Ry, when necessary. The +V cable drive
can be any voltage up to 15 V, and the bus may be run at a lower impedance by selecting pullup resistors for a
static sink current up to 30 mA. V
CC1
and V
CC2
may be chosen to suit the connected devices. Because DDC
uses relatively low speeds (<100 kHz), the cable length is not restricted to 20 m by the I
2
C signaling, but it may
be limited by the video signaling.
Figure 6 and Table 1 show that P82B96 can achieve high clock rates over long cables. While calculating with
lumped wiring capacitance yields reasonable approximations to actual timing; even 25 m of cable is better
treated using transmission line theory. Flat ribbon cables connected as shown, with the bus signals on the outer
edge, have a characteristic impedance in the range 100–200 Ω . For simplicity, they cannot be terminated in their
characteristic impedance, but a practical compromise is to use the minimum pullup allowed for P82B96 and
place half this termination at each end of the cable. When each pullup is below 330 Ω , the rising-edge
waveforms have their first voltage step level above the logic threshold at Rx, and cable timing calculations can
be based on the fast rise/fall times of resistive loading, plus simple one-way propagation delays. When the
pullup is larger, but below 750 Ω , the threshold at Rx is crossed after one signal reflection. So, at the sending
15
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