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Electrical Characteristics
Switching Characteristics
P82B715
I
2
C BUS EXTENDER
SCPS145A – DECEMBER 2007 – REVISED FEBRUARY 2008
V
CC
= 5 V, T
A
= 25 ° C, voltages are specified with respect to GND (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Sx = Sy = V
CC
14
V
CC
= 12 V 15
I
CC
Quiescent supply current mA
Both I
2
C inputs low,
22
Both buffered outputs sinking 30 mA
V
CC
> 3 V,
V
Sx
, V
Sy
(low) = 0.4 V,
I
IOS
Output sink current on I
2
C bus Sx, Sy 2.6 mA
V
Lx
, V
Ly
(low) on buffered bus = 0.3 V,
I
Lx
, I
Ly
= – 3 mA
(1)
V
Lx
, V
Ly
(low) = 0.4 V,
30
V
Sx
, V
Sy
(low) on I
2
C bus = 0.3 V
3 V < V
CC
< 4.5 V,
Output sink current on buffered V
Lx
, V
Ly
(low) = 0.4 V to 1.5 V, 24
I
IOL
Lx, Ly mA
bus I
Sx
, I
Sy
sinking on I
2
C bus < – 4 mA
3 V < V
CC
< 4.5 V,
V
Lx
, V
Ly
(low) = 1.5 V to V
CC
, 24
I
Sx
, I
Sy
sinking on I
2
C bus = – 7 mA
Input current from I
2
C bus Sx, Sy I
Lx
, I
Ly
sink on buffered bus = 30 mA – 3.2
mA
V
CC
> 3 V,
Input current from buffered bus
(1)
– 3
I
Sx
, I
Sy
sink on I
2
C bus = 3 mA
(1)
I
I
Lx, Ly
V
CC
= 3 V to 12 V,
Leakage current on buffered bus V
Lx
, V
Ly
= V
CC
, 200 µ A
V
Sx
, V
Sy
= V
CC
Z
in
/Z
out
Input/output impedance V
Sx
< V
Lx
, Buffer is active 8 10 13
(1) Buffer is passive in this test. The Sx/Sy sink current flows via an internal resistor to the driver connected at the Lx/Ly I/O.
V
CC
= 5 V, T
A
= 25 ° C, no capacitive loads, voltages are specified with respect to GND (unless otherwise specified)
FROM TO
PARAMETER TEST CONDITIONS TYP UNIT
(INPUT) (OUTPUT)
Buffer Delay Times
Delay time to V
Lx
voltage crossing V
CC
/2 for input drive I
Sx
V
Lx
R
Lx
pullup = 270 Ω 250 ns
current step I
Sx
at Sx
(1)
(see Figure 2 ) I
Sy
V
Ly
t
rise/fall
Buffer delay time, switching edges between V
Lx
input and V
Lx
V
Sx
R
Lx
pullup = 4700 Ω 0 ns
V
Sx
output
(2)
V
Ly
V
Sy
(1) A conventional input-output delay is not observed in the Sx/Lx voltage waveforms, because the input and output pins are internally tied
with a 30- Ω resistor so they show equal logic voltage levels to within 100 mV. When connected in an I
2
C system, an Sx/Sy input pin
cannot rise/fall until the buffered bus load at the output pin has been driven by the internal amplifier. This test measures the bus
propagation delay caused to falling or rising voltages at the Lx/Ly output (as well as the Sx/Sy input) by the amplifier ’ s response time.
The figure given is measured with a drive current as shown in Figure 2 . Because this is a dynamic bus test in which a corresponding
bus driving IC has an output voltage well above 0.4 V, 6 mA is used instead of the static 3 mA.
(2) The signal path Lx to Sx and Ly to Sy is passive via the internal 30- Ω resistor. There is no amplifier involved and essentially no signal
propagation delay.
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