Datasheet

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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
V
CC
Lx/LDA
Ly/LCL
GND
Sy/SCL
Sx/SDA
P82B715
Buffer
Buffer
P82B715
I
2
C BUS EXTENDER
SCPS145A – DECEMBER 2007 – REVISED FEBRUARY 2008
In general, the I
2
C bus capacitance limit of 400 pF restricts practical communication distances to a few meters.
One of the advantages of the P82B715 is that it can isolate bus capacitance such that the total loading (devices,
connectors, traces and wires) of the new bus or remote I
2
C nodes are not apparent to other I
2
C buses (or
nodes). This is achieved by using one P82B715 device at each end of a long cable. The pin Lx of one P82B715
device has to be connected to Lx of the second P82B715 (similarly for Ly). This allows the total system
capacitance load to be around 3000 pF. The P82B715 uses unidirectional analog current amplification to
increase the current sink capability of I
2
C chips by a factor of ten and to change the 400-pF I
2
C bus specification
limit into a 4-nF bus wiring capacitance limit. That means longer cables or lower-cost general-purpose wiring may
be used to connect two separate I
2
C-based systems, without worrying about the special voltage levels
associated with other I
2
C bus buffers.
Multiple P82B715s can be connected together in a star or multipoint architecture by their Lx/Ly ports, without
limit, as long as the total capacitance of the system remains less than about 3000 pF (400 pF or less when
referenced to any Sx/Sy connection). In that arrangement, the master and/or slave devices are attached to the
Sx/Sy port of each P82B715. The P82B715 alone does not support voltage-level translation, but it simplifies the
application of low-cost transistors for this purpose. In normal use, the power-supply voltages at each end of the
low-impedance buffered bus line should be the same. If these differ by a significant amount, noise margin is
sacrificed.
Two or more Sx or Sy I/Os can be interconnected and are also fully compatible with bus buffers that use
voltage-level offsets (such as the PCA9515A) because it duplicates and transmits the offset voltage.
TERMINAL FUNCTIONS
D OR P
NAME DESCRIPTION
PACKAGE NO.
1 NC No connection
2 Lx Buffered serial data bus or LDA
3 Sx Serial data bus or SDA. Connect to V
CC
of I
2
C master through a pullup resistor.
4 GND Ground
5 NC No connection
6 Sy Serial clock bus or SCL. Connect to V
CC
of I
2
C master through a pullup resistor.
7 Ly Buffered serial clock bus or LCL
8 V
CC
Supply voltage
FUNCTIONAL BLOCK DIAGRAM
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