Datasheet

General Power Dissipation Considerations
2-9
Evaluation Module Layout
2.6 General Power Dissipation Considerations
For a given θ
JA
, the maximum power dissipation is shown in Figure 2–6 and is calculated by the
following formula:
P
D
T
MAX
–T
A
JA
Where:
P
D
= Maximum power dissipation of Txxxx IC (watts)
T
MAX
= Absolute maximum junction temperature (150°C)
T
A
= Free-air temperature (°C)
θ
JA
= θ
JC
+ θ
CA
θ
JC
= Thermal coefficient from junction to case
θ
CA
= Thermal coefficient from case to ambient air (°C/W)
Figure 2–6. Maximum Power Dissipation vs Free-Air Temperature
T
J
= 150°C
4
3
2
0
–55 –25 5
Maximum Power Dissipation – W
5
6
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
35
1
T
A
– Free-Air Temperature – °C
PWP Package
Low-K Test PCB
θ
JA
= 29.7°C/W
DGN Package
Low-K Test PCB
θ
JA
= 52.3°C/W
PDIP Package
Low-K Test PCB
θ
JA
= 104°C/W
SOT-23 Package
Low-K Test PCB
θ
JA
= 324°C/W
65 95 125
SOIC Package
Low-K Test PCB
θ
JA
= 176°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Table 2–1.Dissipation Rating Table
PACKAGE PowerPAD
θ
JC
(°C/W)
θ
JA
(°C/W)
T
A
≤ 25°C
POWER RATING
DGK (8) 54.23 259.96 424 mW
DGN (8) YES 4.7 52.7 2.37 W
DGS (10) 54.1 257.71 424 mW
DGQ (10) YES 4.7 52.3 2.39 W
PW (16) 28.7 161.4 700 mW
PWP (16) YES 2.07 29.7 4.21 W