Datasheet

BOARD LAYOUT GUIDELINES
OPA860
www.ti.com
....................................................................................................................................................... SBOS331C JUNE 2005 REVISED AUGUST 2008
As a worst-case example, compute the maximum T
J
supplies (for bipolar operation) will improve
using an OPA860ID in the circuit of Figure 53 2nd-harmonic distortion performance. Larger (2.2 µ F
operating at the maximum specified ambient to 6.8 µ F) decoupling capacitors, effective at lower
temperature of +85 ° C and driving a grounded 20 frequency, should also be used on the main supply
load. pins. These may be placed somewhat farther from
the device and may be shared among several
P
D
= 10V × 11.2mA + 5
2
/(4 × 20 ) = 424mW
devices in the same area of the PC board.
Maximum T
J
= +85 ° C + (0.43W × 125 ° C/W) = 139 ° C.
c) Careful selection and placement of external
components will preserve the high-frequency
Although this is still well below the specified
performance of the OPA860. Resistors should be a
maximum junction temperature, system reliability
very low reactance type. Surface-mount resistors
considerations may require lower tested junction
work best and allow a tighter overall layout. Metal film
temperatures. The highest possible internal
or carbon composition, axially-leaded resistors can
dissipation will occur if the load requires current to be
also provide good high-frequency performance.
forced into the output for positive output voltages or
Again, keep their leads and PC board traces as short
sourced from the output for negative output voltages.
as possible. Never use wirewound type resistors in a
This puts a high current through a large internal
high-frequency application.
voltage drop in the output transistors. The output V-I
plot shown in the Typical Characteristics includes a
d) Connections to other wideband devices on the
boundary for 1W maximum internal power dissipation
board may be made with short, direct traces or
under these conditions.
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
Achieving optimum performance with a
preferably with ground and power planes opened up
high-frequency amplifier like the OPA860 requires
around them. If a long trace is required at the buffer
careful attention to board layout parasitics and
output, and the 6dB signal loss intrinsic to a
external component types. Recommendations that
doubly-terminated transmission line is acceptable,
will optimize performance include:
implement a matched impedance transmission line
using microstrip or stripline techniques (consult an
a) Minimize parasitic capacitance to any AC ground
ECL design handbook for microstrip and stripline
for all of the signal I/O pins. Parasitic capacitance on
layout techniques). A 50 environment is normally
the output and inverting input pins can cause
not necessary on board, and in fact, a higher
instability: on the noninverting input, it can react with
impedance environment will improve distortion as
the source impedance to cause unintentional
shown in the distortion versus load plots.
bandlimiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be opened
e) Socketing a high-speed part like the OPA860 is
in all of the ground and power planes around those
not recommended. The additional lead length and
pins. Otherwise, ground and power planes should be
pin-to-pin capacitance introduced by the socket can
unbroken elsewhere on the board.
create an extremely troublesome parasitic network
that makes it almost impossible to achieve a smooth,
b) Minimize the distance ( < 0.25") from the
stable frequency response. Best results are obtained
power-supply pins to high-frequency 0.1 µ F
by soldering the OPA860 onto the board.
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power-supply connections should always be
decoupled with these capacitors. An optional supply
decoupling capacitor (0.1 µ F) across the two power
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