Datasheet

OPA843
17
SBOS268C
www.ti.com
The total output offset voltage may be considerably reduced
by matching the source impedances looking out of the two
inputs. For example, one way to add bias current cancellation
to the circuit of Figure 1 would be to insert a 55Ω series resistor
into the noninverting input from the 50Ω terminating resistor.
When the 50Ω source resistor is DC coupled, this will increase
the source impedance for the noninverting input bias current
to 80Ω. Since this is now equal to the impedance looking out
of the inverting input (R
F
|| R
G
), the circuit will cancel the gains
for the bias currents to the output leaving only the offset
current times the feedback resistor as a residual DC error term
at the output. Using a 402Ω feedback resistor, this output error
will now be less than 1µA • 402Ω = 0.4mV at 25°C.
A fine-scale output offset null, or DC operating point adjust-
ment, is sometimes required. Numerous techniques are
available for introducing a DC offset control into an op amp
circuit. Most of these techniques eventually reduce to setting
up a DC current through the feedback resistor. One key
consideration to selecting a technique is to insure that it has
a minimal impact on the desired signal path frequency
response. If the signal path is intended to be noninverting,
the offset control is best applied as an inverting summing
signal to avoid interaction with the signal source. If the signal
path uses the inverting mode, applying an offset control to
the noninverting input can be considered. For a DC-coupled
inverting input signal, this DC offset signal will set up a DC
current back into the source that must be considered. An
offset adjustment placed on the inverting op amp input can
also change the noise gain and frequency response flatness.
Figure 15 shows one example of an offset adjustment for a
DC-coupled signal path that will have minimum impact on the
signal frequency response. In this case, the input is brought
into an inverting gain resistor with the DC adjustment an
additional current summed into the inverting node. The
resistor values for setting this offset adjustment are chosen
to be much larger than the signal path resistors. This will
insure that this adjustment has minimal impact on the loop
gain and hence, the frequency response.
THERMAL ANALYSIS
The OPA843 will not require heat sinking or airflow in most
applications. Maximum desired junction temperature would
set the maximum allowed internal power dissipation as
described below. In no case should the maximum junction
temperature be allowed to exceed +150°C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
• θ
JA
.
The total internal power dissipation (P
D
) is the sum of quiescent
power (P
DQ
) and additional power dissipated in the output
stage (P
DL
) to deliver load power. Quiescent power is simply
the specified no-load supply current times the total supply
voltage across the part. P
DL
will depend on the required output
signal and load but would, for a grounded resistive load, be at
a maximum when the output is fixed at a voltage equal to 1/2
of either supply voltage (for equal bipolar supplies). Under this
worst-case condition, P
DL
= V
S
2
/(4 • R
L
), where R
L
includes
feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
J
using an
OPA843IDBV (SOT23-5 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85°C. P
D
= 10V(22.5mA) + 5
2
/(4 • (100Ω || 500Ω)) = 300mW.
Maximum T
J
= +85°C + (0.30W • 150°C/W) = 130°C.
mV
< –1.00
< –0.90
Count
1600
1400
1200
1000
800
600
400
200
0
< –0.80
< –0.70
< –0.60
< –0.50
< –0.40
< –0.30
< –0.20
< –0.10
< –0.00
<0.10 <0.20 <0.30 <0.40 <0.50 <0.60 <0.70 <0.80 <1.90 <1.00 >1.00
Mean = 0.04µA
Standard Deviation = 0.17µA
Total Count = 5572
FIGURE 14.
R
F
1kΩ
±125mV Output Adjustment
= – = –4
Power-supply decoupling
not shown.
5kΩ
5kΩ
200Ω
0.1µF
R
G
250Ω
V
IN
20kΩ
10kΩ
0.1µF
–5V
+5V
OPA843
+5V
V
CC
V
EE
–5V
V
O
V
O
V
IN
R
F
R
G
FIGURE 15. DC-Coupled, Inverting Gain of –4 with Output
Offset Adjustment.