Datasheet

-V
CC
+V
CC
External
Pin
+5V
-5V
50W
50W
Power-supply
decoupling not shown.
174W
D1 D2
V
1
301W
R
G
50W
R
F
301W
V
O
D1 = D2 IN5911 (or equivalent)
50 SourceW
OPA842
OPA842
www.ti.com SBOS267D –NOVEMBER 2002–REVISED SEPTEMBER 2010
can create significant time constants that can e) Socketing a high-speed part like the OPA842 is
degrade performance. Good axial metal-film or not recommended. The additional lead length and
surface-mount resistors have approximately 0.2pF in pin-to-pin capacitance introduced by the socket can
shunt with the resistor. For resistor values greater create an extremely troublesome parasitic network,
than 1.5kΩ, this parasitic capacitance can add a pole which can make it almost impossible to achieve a
and/or a zero below 500MHz that can affect circuit smooth, stable frequency response. Best results are
operation. Keep resistor values as low as possible obtained by soldering the OPA842 onto the board.
consistent with load-driving considerations. It has
been suggested here that a good starting point for
INPUT AND ESD PROTECTION
design would be to set R
G
|| R
F
≤ 200Ω. Doing this
The OPA842 is built using a very high speed
will automatically keep the resistor noise terms low,
complementary bipolar process. The internal junction
and minimize the effect of the parasitic capacitance.
breakdown voltages are relatively low for these very
d) Connections to other wideband devices on the
small geometry devices. These breakdowns are
board may be made with short, direct traces or
reflected in the Absolute Maximum Ratings table. All
through onboard transmission lines. For short
device pins have limited ESD protection using internal
connections, consider the trace and the input to the
diodes to the power supplies, as shown in Figure 44.
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set R
S
from the plot of Recommended R
S
vs
Capacitive Load (Figure 15). Low parasitic capacitive
loads (less than 5pF) may not need an R
S
since the
OPA842 is nominally compensated to operate with a
2pF parasitic load. Higher parasitic capacitive loads
without an R
S
are allowed as the signal gain
Figure 44. Internal ESD Protection
increases (increasing the unloaded phase margin). If
a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is
These diodes provide moderate protection to input
acceptable, implement a matched impedance
overdrive voltages above the supplies as well. The
transmission line using microstrip or stripline
protection diodes can typically support 30mA
techniques (consult an ECL design handbook for
continuous current. Where higher currents are
microstrip and stripline layout techniques). A 50Ω
possible (for example, in systems with ±15V supply
environment is normally not necessary on board, and
parts driving into the OPA842), current-limiting series
in fact, a higher impedance environment will improve
resistors should be added into the two inputs. Keep
distortion as shown in the distortion versus load plots.
these resistor values as low as possible since high
With a characteristic board trace impedance defined
values degrade both noise performance and
based on board material and trace dimensions, a
frequency response. Figure 45 shows an example
matching series resistor into the trace from the output
protection circuit for I/O voltages that may exceed the
of the OPA842 is used as well as a terminating shunt
supplies.
resistor at the input of the destination device.
Remember also that the terminating impedance will
be the parallel combination of the shunt resistor and
input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a doubly-
terminated transmission line is unacceptable, a long
trace can be series terminated at the source end
only. Treat the trace as a capacitive load in this case
and set the series resistor value as shown in the plot
of R
S
vs Capacitive Load. This will not preserve
signal integrity as well as a doubly-terminated line. If
the input impedance of the destination device is low,
there will be some signal attenuation due to the
voltage divider formed by the series output into the
terminating impedance.
Figure 45. Gain of +2 with Input Protection
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Product Folder Link(s): OPA842