Datasheet

OPA842
SBOS267D –NOVEMBER 2002–REVISED SEPTEMBER 2010 www.ti.com
DC OFFSET CONTROL P
D
= 10V • 22.5mA + 5
2
/[4 • (100Ω || 800Ω)] =
291mW
The OPA842 can provide excellent dc signal
Maximum T
J
= +85°C + (0.29W • (150°C/W) =
accuracy due to its high open-loop gain, high
129°C
common-mode rejection, high power-supply rejection,
and low input offset voltage and bias current offset
BOARD LAYOUT
errors. To take full advantage of this low input offset
voltage, careful attention to input bias current
Achieving optimum performance with a
cancellation is also required. The high-speed input
high-frequency amplifier such as the OPA842
stage for the OPA842 has a relatively high input bias
requires careful attention to board layout parasitics
current (20mA typ into the pins) but with a very close
and external component types. Recommendations
match between the two input currents—typically
that will optimize performance include:
0.35mA input offset current. The total output offset
a) Minimize parasitic capacitance to any ac
voltage may be considerably reduced by matching
ground for all of the signal I/O pins. Parasitic
the source impedances looking out of the two inputs.
capacitance on the output and inverting input pins
For example, one way to add bias current
can cause instability: on the noninverting input, it can
cancellation to the circuit of Figure 37 would be to
react with the source impedance to cause
insert a 175Ω series resistor into the noninverting
unintentional bandlimiting. To reduce unwanted
input from the 50Ω terminating resistor. When the
capacitance, a window around the signal I/O pins
50Ω source resistor is dc-coupled, this will increase
should be opened in all of the ground and power
the source impedance for the noninverting input bias
planes around those pins. Otherwise, ground and
current to 200Ω. Since this is now equal to the
power planes should be unbroken elsewhere on the
impedance looking out of the inverting input
board.
(R
F
|| R
G
), the circuit will cancel the gains for the bias
currents to the output leaving only the offset current
b) Minimize the distance (< 0.25in., or 0.635cm)
times the feedback resistor as a residual dc error
from the power-supply pins to high-frequency
term at the output. Using a 402Ω feedback resistor,
0.1mF decoupling capacitors. At the device pins,
this output error will now be less than
the ground and power-plane layout should not be in
1mA • 402Ω = 0.4mV at +25°C.
close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance
THERMAL ANALYSIS
between the pins and the decoupling capacitors. The
power-supply connections should always be
The OPA842 will not require heat sinking or airflow in
decoupled with these capacitors. Larger (2.2mF to
most applications. Maximum desired junction
6.8mF) decoupling capacitors, effective at lower
temperature would set the maximum allowed internal
frequency, should also be used on the main supply
power dissipation as described below. In no case
pins. These may be placed somewhat farther from
should the maximum junction temperature be allowed
the device and may be shared among several
to exceed +175°C.
devices in the same area of the PCB.
Operating junction temperature (T
J
) is given by
c) Careful selection and placement of external
T
A
+ P
D
• q
JA
. The total internal power dissipation (P
D
)
components will preserve the high-frequency
is the sum of quiescent power (P
DQ
) and additional
performance of the OPA842. Resistors should be a
power dissipated in the output stage (P
DL
) to deliver
very low reactance type. Surface-mount resistors
load power. Quiescent power is simply the specified
work best and allow a tighter overall layout. Metal-film
no-load supply current times the total supply voltage
and carbon composition, axially leaded resistors can
across the part. PDL will depend on the required
also provide good high-frequency performance.
output signal and load but would, for a grounded
Again, keep the leads and PCB trace length as short
resistive load, be at a maximum when the output is
as possible. Never use wire-wound type resistors in a
fixed at a voltage equal to 1/2 of either supply voltage
highfrequency application. Since the output pin and
(for equal bipolar supplies). Under this worst-case
inverting input pin are the most sensitive to parasitic
condition, P
DL
= V
S2
/(4 • R
L
), where R
L
includes
capacitance, always position the feedback and series
feedback network loading.
output resistor, if any, as close as possible to the
Note that it is the power in the output stage and not in
output pin. Other network components, such as
the load that determines internal power dissipation.
noninverting input termination resistors, should also
be placed close to the package. Where double-side
As a worst-case example, compute the maximum T
J
component mounting is allowed, place the feedback
using an OPA842IDBV (SOT23-5 package) in the
resistor directly under the package on the other side
circuit of Figure 37 operating at the maximum
of the board between the output and inverting input
specified ambient temperature of +85°C.
pins. Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor values
18 Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842