Datasheet
OPA836
Signal and bias
from previous stage
Signal and bias to
next stage
5 V
R
1
R
G
R
F
GV
SIG
0 V
0 V
V
SIG
V
OUT
R
O
R
F
OPA836
Signal and bias
from previous stage
Signal and bias to
next stage
5 V
R
1
R
G
0 V
V
SIG
R
O
V
OUT
GV
SIG
0 V
OPA836
OPA2836
SLOS712E –JANUARY 2011–REVISED SEPTEMBER 2013
www.ti.com
Figure 67. Non-Inverting Single Supply with Pulse
If the input signal pulses negative from ground, an inverting amplifier is more appropriate as shown in Figure 68.
A key consideration in both non-inverting and inverting cases is that the input and output voltages are kept within
the limits of the amplifier, and since the V
ICR
of the OPA836 includes the negative supply rail, the op amp lends
itself to this application.
Figure 68. Inverting Single Supply with Pulse
Power-Down Operation
The OPA836 and OPA2836 include a power-down mode. Under logic control, the amplifiers can be switched
from normal operation to a standby current of <1.5µA. When the PD pin is connected high, the amplifier is active.
Connecting PD pin low disables the amplifier, and places the output in a high impedance state. Note: the op
amp’s output in gain of +1 is high impedance similar to a 3-state high impedance gate, but in other gains the
feedback network is a parallel load.
The PD pin must be actively driven high or low and should not be left floating. If the power-down mode is not
used, PD should be tied to the positive supply rail.
PD logic states are TTL with reference to the negative supply rail, V
S-
. When the op amp is powered from single
supply and ground, driving from logic devices with similar V
DD
voltages to the op amp should not require any
special consideration. When the op amp is powered from split supply, V
S-
is below ground and an open collector
type of interface with pull-up resistor is more appropriate. Pull-up resistor values should be lower than 100k and
the drive logic should be negated due to the inverting action of an open collector gate.
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